®
ISL7124SRH
Data Sheet
September 2002
FN9090
Single-Event Hardened, Single Supply,
Quad Operational Amplifier
The single-event radiation hardened ISL7124SRH consists
of four independent, high gain, internally frequency
compensated operational amplifiers, specifically designed to
operate from a single power supply over a wide range of
voltages. The device is functionally equivalent to industry
standard 124 types, offering improvements in supply current
and power supply rejection ratio.
Constructed with Intersil’s dielectrically isolated, radiation
hardened silicon gate (RSG) BiCMOS process, these
devices are immune to single event latchup. Additionally, the
design has been hardened to prevent single event transients
(SETs) in excess of 1V for LETs up to 36MeV/mg/cm
2
.
The ISL7124SRH has been specifically designed and
manufactured to provide highly reliable performance in
harsh radiation environments. It is total dose hardened to
300krad(Si) and offers guaranteed performance over the full
-55C to +125C military temperature range.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-02542. A “hot-link” is provided
on our website for downloading.
Features
• QML Qualified per MIL-PRF-38535 Requirements
• Electrically Screened to DSCC SMD # 5962-02542
• Radiation Environment
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 300krad(Si)(Max)
- Latch-Up Immune
- SET Threshold (Delta Vo<1V) . . . 36MeV/mg/cm
2
(Min)
• Single Supply Voltage Range (5V to 30V)
• Input Common Mode Voltage Range Includes Ground
• Input Offset Voltage . . . . . . . . . . . . . . . . . . +/-10mV(Max)
• Input Offset Current . . . . . . . . . . . . . . . . . . +/-150nA(Max)
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . 400nA(Max)
• Open Loop Voltage Gain . . . . . . . . . . . . . . . 20V/mV(Min)
• Power Supply Rejection Ratio . . . . . . . . . . . . . .70dB(Min)
• Common Mode Rejection Ratio . . . . . . . . . . . . .70dB(Min)
• ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V(Min)
Applications
• Single Supply Operation of Op-Amp Circuits
• General Analog Signal Processing
Ordering Information
ORDERING NUMBER
5962F0254201VXC
INTERNAL
MKT. NUMBER
ISL7124SRHVF
ISL7124SRHQF
ISL7124SRHF/Proto
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
Pinout
ISL7124SRHF (FLATPACK CDFP3-F14)
TOP VIEW
OUT 1
-IN 1
+IN 1
+V
CC
+IN 2
-IN 2
OUT 2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT 4
-IN 4
+IN 4
-V
CC
+IN 3
-IN 3
OUT 3
5962F0254201QXC
ISL7124SRHF/Proto
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ISL7124SRH
Die Characteristics
DIE DIMENSIONS:
2640µm x 5020µm (104 mils x 198mils)
Thickness: 483µm
±
25.4µm (19 mils
±
1 mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ
±
1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ
±
2kÅ
Substrate:
Radiation Hardened Silicon Gate
Dielectrically Isolated
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
276
Metallization Mask Layout
ISL7124SRH
-V
CC
-IN 4
+IN 4
+IN 3
-IN 3
OUT 4
OUT 3
Layout not yet available.
OUT 1
OUT 2
-IN 1
+IN 1
+IN 2
+V
CC
-IN 2
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
2
Power technology
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