74FST3383
10-Bit Low Power
Bus Exchange
The ON Semiconductor 74FST3383 is a 10–bit low power bus
exchange. The device is CMOS TTL compatible when operating
between 4 and 5.5 Volts. The device exhibits extremely low RON and
adds nearly zero propagation delay. The device adds no noise or
ground bounce to the system.
•
RON
t
4
W
Typical
•
Less Than 0.25 ns–Max Delay Through Switch
•
Nearly Zero Standby Current
•
No Circuit Bounce
•
Control Inputs are TTL/CMOS Compatible
•
Pin–For–Pin Compatible With QS3383, FST3383, CBT3383
•
All Popular Packages: QSOP–24, TSSOP–24, SOIC–24
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MARKING
DIAGRAMS
24
24
1
SO–24
D SUFFIX
CASE 751E
1
FST3383
AWLYWW
OE
C0
A0
B0
D0
C1
A1
B1
D1
C2
A2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
D4
B4
A4
C4
D3
B3
A3
C3
D2
B2
BX
24
24
1
TSSOP–24
DT SUFFIX
CASE 948H
1
FST
3383
ALYW
24
24
1
QSOP–24
QS SUFFIX
CASE 492B
Function
Disconnect
Connect
Exchange
A
L, WL
Y, YY
W, WW
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
FST3383
AWLYYWW
1
Figure 1. 24–Lead Pinout
OE
H
L
L
BX
X
L
H
A0–A4
HIGH–Z State
C0–C4
D0–D4
B0–B4
HIGH–Z State
D0–D4
C0–C4
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care
Figure 2. Truth Table
ORDERING INFORMATION
Device
74FST3383D
Package
SO–24
SO–24
TSSOP–24
TSSOP–24
QSOP–24
QSOP–24
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
PIN NAMES
Pin
OE
BX
A0–A4, B0–B4
C0–C4, D0–D4
Description
Bus Switch Enable
Bus Exchange
Buses A, B
Buses C, D
74FST3383DR2
74FST3383DT
74FST3383DTR2
74FST3383QS
74FST3383QSR
©
Semiconductor Components Industries, LLC, 2002
1
February, 2002 – Rev. 2
Publication Order Number:
74FST3383/D
74FST3383
A0
C0
B0
D0
A4
C4
B4
D4
BX
OE
Figure 3. Logic Diagram
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2
74FST3383
MAXIMUM RATINGS
Symbol
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
TL
TJ
q
JA
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
SOIC
TSSOP
QSOP
VI
t
GND
VO
t
GND
Parameter
Value
*0.5
to
)7.0
*0.5
to
)7.0
*0.5
to
)7.0
*50
*50
128
$100
$100
*65
to
)150
260
)150
125
170
200
Level 1
Oxygen Index: 28 to 34
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above VCC and Below GND at 85_C (Note 4)
UL 94 V–0 @ 0.125 in
u2000
u200
N/A
$500
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
MSL
FR
VESD
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
ILATCH–UP
Latch–Up Performance
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Tested to EIA/JESD22–A114–A.
2. Tested to EIA/JESD22–A115–A.
3. Tested to JESD22–C101–A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
VO
TA
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free–Air Temperature
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
VCC = 5.0 V
$
0.5 V
Parameter
Operating, Data Retention Only
(Note 5)
(HIGH or LOW State)
Min
4.0
0
0
*40
0
Max
5.5
5.5
5.5
)85
DC
5
Unit
V
V
V
_C
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
74FST3383
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
VIK
VIH
VIL
II
IOZ
RON
Parameter
Clamp Diode Resistance
High–Level Input Voltage
Low–Level Input Voltage
Input Leakage Current
OFF–STATE Leakage Current
Switch On Resistance (Note 6)
0
v
VIN
v
5.5 V
0
v
A, B
v
VCC
VIN = 0 V, IIN = 64 mA
VIN = 0 V, IIN = 30 mA
VIN = 2.4 V, IIN = 15 mA
VIN = 2.4 V, IIN = 15 mA
ICC
DI
CC
Quiescent Supply Current
Increase In ICC per Input
VIN = VCC or GND, IOUT = 0
One input at 3.4 V, Other inputs at VCC or GND
IIN =
*18mA
Conditions
(V)
4.5
4.0 to 5.5
4.0 to 5.5
5.5
5.5
4.5
4.5
4.5
4.0
5.5
5.5
4
4
8
11
2.0
0.8
$1.0
$1.0
7
7
15
20
3
2.5
mA
mA
TA =
*40_C
to
)85_C
Min
Typ*
Max
*1.2
Unit
V
V
V
mA
mA
W
*Typical values are at VCC = 5.0 V and TA = 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA =
*40_C
to
)85_C
CL = 50 pF, RU = RD = 500
W
VCC = 4.5–5.5 V
Symbol
tPHL,PLH
t
Parameter
Prop Delay Bus to Bus (Note 7)
Prop Delay, BX to An, Bn, Cn or Dn
tPZH,t
PZL
Output Enable Time, BX to An, Bn, Cn or Dn
Output Enable Time, IOE to An, Bn, Cn or Dn
tPHZ,t
PLZ
Output Disable Time, BX to An, Bn, Cn or Dn
Output Disable Time, IOE to An, Bn, Cn or Dn
VI = 7 V for tPZL
VI = OPEN for tPZH
VI = 7 V for tPLZ
VI = OPEN for tPHZ
Conditions
VI = OPEN
1.0
1.0
1.0
1.0
1.0
Min
Max
0.25
5.8
5.8
5.8
5.3
5.3
VCC = 4.0 V
Min
Max
0.25
6.5
6.5
6.5
6.2
6.2
ns
ns
Unit
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE
(Note 8)
Symbol
CIN
CI/O
Parameter
Control Pin Input Capacitance
Port Input/Output Capacitance
VCC = 5.0 V
VCC, OE = 5.0 V
Conditions
Typ
6
13
Max
Unit
pF
pF
8. TA =
)25_C,
f = 1 MHz, Capacitance is characterized but not tested.
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4
74FST3383
AC Loading and Waveforms
VI
FROM
OUTPUT
UNDER
TEST
CL*
500
W
500
W
NOTES:
1. Input driven by 50
W
source terminated in 50
W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 4. AC Test Circuit
tf = 2.5 nS
90 %
SWITCH
INPUT
1.5 V
10 %
tPLH
90 %
1.5 V
tf = 2.5 nS
3.0 V
10 %
tPLH
GND
VOH
1.5 V
OUTPUT
1.5 V
VOL
Figure 5. Propagation Delays
tf = 2.5 nS
tf = 2.5 nS
ENABLE
INPUT
90 %
1.5 V
10 %
tPZL
OUTPUT
10 %
90 %
1.5 V
GND
tPZL
3.0 V
1.5 V
VOL + 0.3 V
VOL
tPHZL
VOH
tPZH
1.5 V
OUTPUT
VOH – 0.3 V
Figure 6. Enable/Disable Delays
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5
Embedded System
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