ispLSI2032VL-180LB49 datasheet, PDF

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ispLSI2032VL-180LB49: Description2.5V In-System Programmable SuperFAST⑩ High Density PLD; CategoryProgrammable logic devices Programmable logic; File Size116KB，12 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ispLSI2032VL-180LB49 Overview

2.5V In-System Programmable SuperFAST⑩ High Density PLD

ispLSI2032VL-180LB49 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	CABGA-49
Contacts	49
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	YES
maximum clock frequency	118 MHz
In-system programmable	YES
JESD-30 code	S-PBGA-B49
JESD-609 code	e0
JTAG BST	YES
length	7 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	49
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA49,7X7,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5 V
Programmable logic type	EE PLD
propagation delay	5 ns
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	7 mm
Base Number Matches	1

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ispLSI 2032VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2032V and 2032VE Devices

• 2.5V LOW VOLTAGE 2032 ARCHITECTURE

— Interfaces With Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 45 mA Typical Active Current

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 180 MHz Maximum Operating Frequency

—

= 5.0 ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool (ORP)

Input Bus

GLB

Logic

Array

D Q

0139Bisp/2000

Description

The ispLSI 2032VL is a High Density Programmable

Logic Device containing 32 Registers, 32 Universal I/O

pins, two Dedicated Input Pins, three Dedicated Clock

Input Pins, one dedicated Global OE input pin and a

Global Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 2032VL features in-system programmability

through the Boundary Scan Test Access Port (TAP) and

is 100% IEEE 1149.1 Boundary Scan Testable. The

ispLSI 2032VL offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 2032VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2032vl_02

Input Bus

D Q

Output Routing Pool (ORP)

Global Routing Pool

(GRP)

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