ispLSI 2064V
3.3V High Density Programmable Logic
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with
5V ispLSI 2064
HIGH-PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 100MHz Maximum Operating Frequency
—
t
pd
= 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Input Bus
®
Functional Block Diagram
Output Routing Pool (ORP)
A0
Output Routing Pool (ORP)
•
Input Bus
A2
GLB
Logic
Array
D Q
D Q
B1
D
D Q
•
A3
A4
A5
B0
A7
EW
A6
Output Routing Pool (ORP)
Input Bus
N
•
0139A/2064V
SI
20
64
•
VE
U
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
pL
FO
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
R
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2064v_10
1
Input Bus
A1
D Q
B2
Output Routing Pool (ORP)
ES
IG
Global Routing Pool
(GRP)
N
B3
S
B7
B6
B5
B4
Specifications
ispLSI 2064V
Functional Block Diagram
Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions)
GOE 0
GOE 1
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 31
I/O 30
I/O 29
I/O 28
Input Bus
Generic Logic
Blocks (GLBs)
I/O 27
I/O 26
I/O 25
I/O 24
Input Bus
Megablock
B7
Output Routing Pool (ORP)
B6
B5
B4
Megablock
B7
Output Routing Pool (ORP)
B6
B5
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
A2
B1
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
TCK/IN 3
TDO/IN 2
I/O 4
I/O 5
I/O 6
I/O 7
TDI/IN 0
TDO/IN 1
A2
D
A4
A5
A6
A7
B1
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A1
Global Routing Pool
(GRP)
B2
I/O 43
I/O 42
I/O 41
I/O 40
A1
Global Routing Pool
(GRP)
B2
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 47
ES
IG
B3
B0
N
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
GOE0/IN 3
TMS/IN 2
A0
B3
I/O 46
I/O 45
I/O 44
I/O 0
I/O 1
I/O 2
I/O 3
A0
A3
B0
A3
A4
A5
A6
A7
CLK 0
CLK 1
CLK 2
ispEN
Input Bus
ispEN
Input Bus
Y0
Y1
Y2
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
U
SE
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064V device contains
two Megablocks.
is
pL
SI
2
The 64-I/O 2064V contains 64 I/O cells, while the 32-I/O
version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
4V
E
06
FO
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064V are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
2
GOE1/Y0
RESET/Y1
TCK/Y2
0139B/2064V
R
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
CLK 0
CLK 1
CLK 2
0139B/2064V.32IO
RESET
N
Output Routing Pool (ORP)
EW
Output Routing Pool (ORP)
S
Generic Logic
Blocks (GLBs)
Specifications
ispLSI 2064V
Absolute Maximum Ratings
1
Supply Voltage V
cc ...................................................
-0.5 to +5.6V
Input Voltage Applied ..................................... -0.5 to +5.6V
Off-State Output Voltage Applied .................. -0.5 to +5.6V
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
DC Recommended Operating Condition
D
MIN.
3.0
3.0
V
SS
– 0.5
2.0
MAX.
3.6
3.6
0.8
5.25
UNITS
V
V
V
V
Table 2-0005/2064V
V
CC
V
IL
V
IH
T
A
= -40°C to + 85°C
4V
E
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
FO
R
N
T
A
= 0°C to + 70°C
TYPICAL
10
10
13
UNITS
pf
pf
pf
SI
2
C
1
C
2
C
3
06
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
pL
Data Retention Specifications
PARAMETER
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008/2064V
Data Retention
ispLSI Erase/Reprogram Cycles
U
SE
is
3
ES
IG
TEST CONDITIONS
V
CC
= 3.3V, V
IN
= 2.0V
V
CC
= 3.3V, V
I/O
= 2.0V
V
CC
= 3.3V, V
Y
= 2.0V
Table 2-0006/2064V
N
S
Storage Temperature ..................................... -65 to 150°C
Specifications
ispLSI 2064V
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
≤
1.5 ns
1.5V
1.5V
See Figure 2
Table 2-0003/2064V
Figure 2. Test Load
+ 3.3V
R1
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
316Ω
∞
316Ω
∞
316Ω
R2
348Ω
348Ω
348Ω
348Ω
348Ω
CL
35pF
35pF
35pF
5pF
5pF
D
MIN.
–
2.4
–
–
–
–
–
–
–
*
CL includes Test Fixture and Probe Capacitance.
0213A/2064V
Table 2-0004/2064V
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Over Recommended Operating Conditions
E
FO
R
N
C
EW
CONDITION
06
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
4V
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
ES
IG
R2
C L
*
TYP.
–
–
–
–
–
–
–
–
82
3
MAX. UNITS
0.4
–
-10
10
50
-150
-150
-100
–
V
V
µA
µA
mA
µA
µA
mA
mA
Input or I/O Low Leakage Current
SI
2
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
(V
CC
– 0.2)V
≤
V
IN
≤
V
CC
V
≤
V
IN
≤
5.25V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 3.3V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Output Short Circuit Current
Table 2-0007/2064V
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 3.3V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
U
SE
is
Operating Power Supply Current
pL
4
N
Device
Output
S
Test
Point
Specifications
ispLSI 2064V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
DESCRIPTION
1
-100
–
–
3
1
-80
–
–
80.0
64.5
100
7.0
–
10.0
15.0
–
–
–
–
–
–
-60
15.0
20.0
–
–
–
–
–
–
–
16.0
–
18.0
18.0
12.0
12.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
7.5
12.0
–
–
–
–
5.0
–
–
–
–
6.3
UNITS
ns
ns
MHz
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Clock Frequency with External Feedback
(
tsu2 + tco1
)
102
83.3
125
5.5
–
0.0
7.0
–
0.0
–
–
–
–
–
4.0
4.0
5.0
61.7
51.3
71.4
9.0
–
0.0
–
0.0
–
8.0
–
–
–
–
7.0
7.0
N
8.5
9.5
ES
IG
6.5
–
–
–
14.0
–
15.0
15.0
10.0
10.0
–
–
11.0
–
–
7.5
–
–
–
–
0.0
9.0
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
D
0.0
7.0
5.0
5.0
EW
12.0
13.0
13.0
7.5
7.5
–
–
N
R
FO
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
E
U
SE
is
pL
SI
2
06
4V
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030/2064V
5
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
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