ispLSI2096VL-165LT128 datasheet, PDF

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ispLSI2096VL-165LT128: Description2.5V In-System Programmable SuperFAST⑩ High Density PLD; CategoryProgrammable logic devices Programmable logic; File Size110KB，11 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ispLSI2096VL-165LT128 Overview

2.5V In-System Programmable SuperFAST⑩ High Density PLD

ispLSI2096VL-165LT128 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	TQFP-128
Contacts	128
Reach Compliance Code	_compli
ECCN code	EAR99
Other features	YES
maximum clock frequency	118 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G128
JESD-609 code	e0
JTAG BST	YES
length	14 mm
Humidity sensitivity level	3
Dedicated input times	2
Number of I/O lines	96
Number of macro cells	96
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2 DEDICATED INPUTS, 96 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP128,.64SQ,16
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5 V
Programmable logic type	EE PLD
propagation delay	8 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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ispLSI 2096VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 4000 PLD Gates

— 96 I/O Pins, Six Dedicated Inputs

— 96 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2096V and 2096VE Devices

• 2.5V LOW VOLTAGE 2096 ARCHITECTURE

— Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 85 mA Typical Active Current

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 165 MHz Maximum Operating Frequency

—

= 5.5 ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Output Routing Pool (ORP)

D Q

GLB

Logic

Array

D Q

Global Routing Pool

(GRP)

D Q

Output Routing Pool (ORP)

0919/2096VL

Description

The ispLSI 2096VL is a High Density Programmable

Logic Device containing 96 Registers, six Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2096VL fea-

tures in-system programmability through the Boundary

Scan Test Access Port (TAP) and is 100% IEEE 1149.1

Boundary Scan Testable. The ispLSI 2096VL offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2096VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. C7 (see Figure 1). There are a total of 24 GLBs in the

ispLSI 2096VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

The devices also have 96 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

output or bi-directional I/O pin with 3-state control, and

the output drivers can source 4 mA or sink 8 mA. Each

output can be programmed independently for fast or slow

output slew rate to minimize overall output switching

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2096vl_02

Output Routing Pool (ORP)

ispLSI2096VL-165LT128 Related Products

	ispLSI2096VL-165LT128	ISPLSI2096VL	2096VL	ispLSI2096VL-135LT128	ispLSI2096VL-100LT128
Description	2.5V In-System Programmable SuperFAST⑩ High Density PLD	2.5V In-System Programmable SuperFAST⑩ High Density PLD	2.5V In-System Programmable SuperFAST⑩ High Density PLD	2.5V In-System Programmable SuperFAST⑩ High Density PLD	2.5V In-System Programmable SuperFAST⑩ High Density PLD
Is it Rohs certified?	incompatible	-	-	incompatible	incompatible
Parts packaging code	QFP	-	-	QFP	QFP
package instruction	TQFP-128	-	-	TQFP-128	TQFP-128
Contacts	128	-	-	128	128
Reach Compliance Code	_compli	-	-	_compli	_compli
ECCN code	EAR99	-	-	EAR99	EAR99
Other features	YES	-	-	YES	YES
maximum clock frequency	118 MHz	-	-	95 MHz	77 MHz
In-system programmable	YES	-	-	YES	YES
JESD-30 code	S-PQFP-G128	-	-	S-PQFP-G128	S-PQFP-G128
JESD-609 code	e0	-	-	e0	e0
JTAG BST	YES	-	-	YES	YES
length	14 mm	-	-	14 mm	14 mm
Humidity sensitivity level	3	-	-	3	3
Dedicated input times	2	-	-	2	2
Number of I/O lines	96	-	-	96	96
Number of macro cells	96	-	-	96	96
Number of terminals	128	-	-	128	128
Maximum operating temperature	70 °C	-	-	70 °C	70 °C
organize	2 DEDICATED INPUTS, 96 I/O	-	-	2 DEDICATED INPUTS, 96 I/O	2 DEDICATED INPUTS, 96 I/O
Output function	MACROCELL	-	-	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	-	-	LFQFP	LFQFP
Encapsulate equivalent code	QFP128,.64SQ,16	-	-	QFP128,.64SQ,16	QFP128,.64SQ,16
Package shape	SQUARE	-	-	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	-	-	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240	-	-	240	240
power supply	2.5 V	-	-	2.5 V	2.5 V
Programmable logic type	EE PLD	-	-	EE PLD	EE PLD
propagation delay	8 ns	-	-	10 ns	13 ns
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	-	-	1.6 mm	1.6 mm
Maximum supply voltage	2.7 V	-	-	2.7 V	2.7 V
Minimum supply voltage	2.3 V	-	-	2.3 V	2.3 V
Nominal supply voltage	2.5 V	-	-	2.5 V	2.5 V
surface mount	YES	-	-	YES	YES
technology	CMOS	-	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	-	-	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	-	-	GULL WING	GULL WING
Terminal pitch	0.4 mm	-	-	0.4 mm	0.4 mm
Terminal location	QUAD	-	-	QUAD	QUAD
Maximum time at peak reflow temperature	30	-	-	30	30
width	14 mm	-	-	14 mm	14 mm
Base Number Matches	1	-	-	1	1

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