ISPLSI2128V-60LQ160 datasheet, PDF

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ISPLSI2128V-60LQ160: Description3.3V High Density Programmable Logic; CategoryProgrammable logic devices Programmable logic; File Size149KB，15 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPLSI2128V-60LQ160 Overview

3.3V High Density Programmable Logic

ISPLSI2128V-60LQ160 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	PLASTIC, QFP-160
Contacts	160
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	YES
maximum clock frequency	51.3 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G160
JESD-609 code	e0
JTAG BST	NO
length	28 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	128
Number of macro cells	128
Number of terminals	160
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 128 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP160,1.2SQ
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Programmable logic type	EE PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm

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ispLSI 2128V

3.3V High Density Programmable Logic

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

—

6000 PLD Gates

128 and 64 I/O Pin Versions, Eight Dedicated Inputs

128 Registers

High Speed Global Interconnect

Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Output Routing Pool (ORP)

Functional Block Diagram*

Output Routing Pool (ORP)

• 3.3V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

— The 128 I/O Pin Version is Fuse Map Compatible

with 5V ispLSI 2128

• HIGH PERFORMANCE E CMOS TECHNOLOGY

—

GLB

Output Routing Pool (ORP)

max

= 80 MHz Maximum Operating Frequency

= 10 ns Propagation Delay

Electrically Erasable and Reprogrammable

Non-Volatile

100% Tested at Time of Manufacture

Unused Product Term Shutdown Saves Power

Output Routing Pool (ORP)

Global Routing Pool (GRP)

Output Routing Pool (ORP)

*128 I/O Version Shown

CLK 0

CLK 1

CLK 2

0139A/2128V

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

—

Enhanced Pin Locking Capability

Three Dedicated Clock Input Pins

Synchronous and Asynchronous Clocks

Programmable Output Slew Rate Control

Flexible Pin Placement

Optimized Global Routing Pool Provides Global

Interconnectivity

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

The ispLSI 2128V is a High Density Programmable Logic

Device available in 128 and 64 I/O-pin versions. The

device contains 128 Registers, eight Dedicated Input

pins, three Dedicated Clock Input pins, two dedicated

Global OE input pins and a Global Routing Pool (GRP).

The GRP provides complete interconnectivity between

all of these elements. The ispLSI 2128V features in-

system programmability through the Boundary Scan

Test Access Port (TAP). The ispLSI 2128V offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128V device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• IN-SYSTEM PROGRAMMABLE

Description

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2128v_14

Output Routing Pool (ORP)

Logic

Array

Output Routing Pool (ORP)

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