Standard Products
UT699 32-bit Fault-Tolerant
SPARC
TM
V8/LEON 3FT Processor
Preliminary Data Sheet
January 7, 2009
FEATURES
Implemented on a 0.25μm CMOS technology
Flexible static design allows up to 75MHz clock rate
Internally configured clock network
On-board programmable timers and interrupt controllers
High-performance fully pipelined IEEE-754 FPU
Power saving 2.5V core power supply
3.3V I/O compatibility
Separate instruction and data cache architecture
10T/100 Ethernet port for VxWorks development
Integrated PCI 2.2 compliant core
Integrated multi-protocol SpaceWire core supports RMAP,
GAP and GRDDP with node and router functions
CAN compliant 2.0 standard bus
-40
o
C to +105
o
C temperature range
Operational environment:
- Intrinsic total-dose: 100 krad((Si) and 300 krad (Si)
- SEL Immune >110 MeV-cm
2
/mg
Packaging options:
- 352-pin Ceramic Quad Flatpack, weight 31.5 grams
Standard Microcircuit Drawing 5962-08228
- QML Q and V
Applications
- Nuclear power plant controls
- Critical transportation systems
- High-altitude avionics
- Medical electronics
- X-Ray cargo scanning
INTRODUCTION
The UT699 is a pipelined monolithic, high-performance, fault-
tolerant SPARC
TM
V8/LEON 3FT Processor. The UT699
provides a 32-bit master/target PCI interface, including a 16 bit
user I/O interface for off-chip peripherals. A compliant 2.0
AMBA bus interface integrates the on-chip LEON 3FT,
SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and
programmable interrupt peripherals.
The UT699 is SPARC V8 compliant; compilers and kernels for
SPARC V8 can therefore be used industry standard
development tools. A full software development suite is
available including a C/C++ cross-compiler system based on
GCC and the Newlib embedded C-library.
BCC includes a small run-time kernel with interrupt support
and Pthreads library. For multi-threaded applications, a
SPARC
TM
compliant port of the eCos real-time kernel, RTEMS
4.6.5, and VxWorks 6.x is supported.
1
1.0 Introduction
The UT699 LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the
SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA
(Advanced Microcontroller Bus Architecture) backplane. This bus is comprised of the AHB (Advanced High-speed Bus) which is
used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.
IEEE754
FPU
MUL/DIV
LEON 3FT
2x4K
D-cache
2x4K
I-cache
Debug
Support Unit
Serial/JTAG
Debug Link
4x SpW
PCI
Bridge
CAN-2.0
MMU
AHB interface
AMBA AHB
AHB Ctrl
Memory
Controller
AHB/APB
Bridge
UART
AMBA APB
Timers
IrqCtrl
I/O port
Ethernet
MAC
8/32-bits memory bus
512 MB
PROM
512 MB
I/O
Up t o1GB
SRAM
Up to 1GB
SDRAM
Figure 1. UT699 Functional Block Diagram
The LEON 3FT architecture includes the following peripheral blocks:
• LEON3 SPARC V8 integer unit with 8kB instruction cache and 8kB of data cache
• IEEE-754 floating point unit
• Debug support unit
• UART and JTAG debug links
• 8/16/32-bit memory controller with EDAC for external PROM and SRAM
• 32-bit SDRAM controller with EDAC for external SDRAM
• Timer unit with three 32-bit timers and watchdog
• Interrupt controller for 15 interrupts in two priority levels
• 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources
• AMBA AHB status register
• Up to four SpaceWire links with RMAP on channels 1 and 2
• Up to two CAN controllers
• Ethernet with support for MII
• cPCI interface with 8-channel arbiter
2
2.0 Pin Identification and Description
Pin Function
I
IS
O
I/O
OD
PCI-I
PCI-O
PCI-I/O
PCI-3
2.1. System Signals
Pin
Number
88
136
142
145
Reset
Value
--
--
--
--
Description
CMOS input
CMOS input Schmitt
CMOS output
CMOS bi-direct
CMOS open drain
PCI input
PCI output
PCI bi-direct
PCI three-state
Pin Name
SYSCLK
RESET
ERROR
1
WDOG
1
Function
I
IS
OD
OD
Description
Main system clock
System reset
Processor error mode indicator. This is an
active low output.
Watchdog indicator. This is an active low
output.
Notes:
1. This pin is actively driven low and must be tied to V
DD
through a pull-up resistor.
2.2 Address Bus
Pin
Number
1
2
4
5
6
7
9
10
11
12
16
Reset
Value
Pin Name
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
Direction
O
O
O
O
O
O
O
O
O
O
O
Description
Bit 0 of the address bus
Bit 1 of the address bus
Bit 2 of the address bus
Bit 3 of the address bus
Bit 4 of the address bus
Bit 5 of the address bus
Bit 6 of the address bus
Bit 7 of the address bus
Bit 8 of the address bus
Bit 9 of the address bus
Bit 10 of the address bus
3
Pin Name
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[17]
ADDR[18]
ADDR[19]
ADDR[20]
ADDR[21]
ADDR[22]
ADDR[23]
ADDR[24]
ADDR[25]
ADDR[26]
ADDR[27]
Direction
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Pin
Number
17
18
19
21
22
23
24
26
27
28
29
31
32
33
34
38
39
Reset
Value
Description
Bit 11 of the address bus
Bit 12 of the address bus
Bit 13 of the address bus
Bit 14 of the address bus
Bit 15 of the address bus
Bit 16 of the address bus
Bit 17 of the address bus
Bit 18 of the address bus
Bit 19 of the address bus
Bit 20 of the address bus
Bit 21 of the address bus
Bit 22 of the address bus
Bit 23 of the address bus
Bit 24 of the address bus
Bit 25 of the address bus
Bit 26 of the address bus
Bit 27 of the address bus
2.3 Data Bus
Pin
Number
43
45
46
47
48
50
51
52
53
Reset
Value
Pin Name
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
Direction
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Bit 0 of the data bus
Bit 1 of the data bus
Bit 2 of the data bus
Bit 3 of the data bus
Bit 4 of the data bus
Bit 5 of the data bus
Bit 6 of the data bus
Bit 7 of the data bus
Bit 8 of the data bus
4
Pin Name
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[16]
DATA[17]
DATA[18]
DATA[19]
DATA[20]
DATA[21]
DATA[22]
DATA[23]
DATA[24]
DATA[25]
DATA[26]
DATA[27]
DATA[28]
DATA[29]
DATA[30]
DATA[31]
2.4 Check Bits
Direction
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin
Number
57
58
59
60
62
63
64
66
67
68
69
71
72
73
74
78
79
80
81
83
84
85
86
Reset
Value
Description
Bit 9 of the data bus
Bit 10 of the data bus
Bit 11 of the data bus
Bit 12 of the data bus
Bit 13 of the data bus
Bit 14 of the data bus
Bit 15 of the data bus
Bit 16 of the data bus
Bit 17 of the data bus
Bit 18 of the data bus
Bit 19 of the data bus
Bit 20 of the data bus
Bit 21 of the data bus
Bit 22 of the data bus
Bit 23 of the data bus
Bit 24 of the data bus
Bit 25 of the data bus
Bit 26 of the data bus
Bit 27 of the data bus
Bit 28 of the data bus
Bit 29 of the data bus
Bit 30 of the data bus
Bit 31 of the data bus
Pin Name
CB[0]
CB[1]
CB[2]
CB[3]
Direction
I/O
I/O
I/O
I/O
Pin
Number
89
90
91
92
Reset
Value
Description
Bit 0 of EDAC checkbits
Bit 1 of EDAC checkbits
Bit 2 of EDAC checkbits
Bit 3 of EDAC checkbits
5
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