TECHNICAL DATA
IW4019B
Quad AND/OR Select Gate
High-Voltage Silicon-Gate CMOS
The IW4019B types consist of four AND/OR select gate
configurations, each consisting of two 2-input AND gates driving a single
2-input gate. Selection is accomplished by control bits S
a
and S
b
.In
addition to selection of either channel A or channel B information, the
control bits can be applied simultaneously to accomplish the logical A + B
function
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4019BN Plastic
IW4019BDW SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
S
a
H
H
L
L
L
H
H
PIN 16 =V
CC
PIN 8 = GND
H
H
S
b
L
L
H
H
L
H
H
H
H
A
H
L
X
X
X
L
L
H
H
B
X
X
H
L
X
L
H
L
H
Outputs
Y
H
L
H
L
L
L
H
H
H
1
IW4019B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IW4019B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Minimum Output
Low (Sink) Current
Test Conditions
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
V
IN
=GND or V
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
Guaranteed Limit
≥-55°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
1
2
4
20
0.64
1.6
4.2
-2.0
-0.64
-1.6
-4.2
25°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
1
2
4
20
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
≤125
°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±1.0
30
60
120
600
0.36
0.9
2.4
mA
-1.15
-0.36
-0.9
-2.4
Unit
V
V
IL
V
V
OH
V
V
OL
V
IN
=GND or V
CC
V
I
IN
I
CC
V
IN
= GND or V
CC
V
IN
= GND or V
CC
µA
µA
I
OL
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
mA
I
OH
Minimum Output
V
IN
= GND or V
CC
High (Source) Current U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
3
IW4019B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200KΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A, B, S
A
or
S
b
to Output Y (Figure 1)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
All A and B
Inputs
S
a
and S
b
Inputs
V
5.0
10
15
5.0
10
15
-
-
300
120
100
200
100
80
Guaranteed Limit
≥-55°C
25°C
300
120
100
200
100
80
7.5
15.0
≤125°C
600
240
200
400
200
160
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
4
IW4019B
N SUFFIX PLASTIC
(MS - 001BB)
A
16
9
B
1
8
Dimensions, mm
Symbol
A
B
MIN
18.67
6.10
0.36
1.14
2.54
7.62
0°
2.92
7.62
0.20
0.38
10°
3.81
8.26
0.36
MAX
19.69
7.11
5.33
0.56
1.78
F
L
C
D
F
C
-T-
SEATING
PLANE
N
G
D
0.25 (0.010) M T
K
M
H
J
G
H
J
K
L
M
N
NOTES:
1. imensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC
(MS - 012AC)
A
16
9
Dimensions, mm
Symbol
.
MIN
9.80
3.80
1.35
0.33
0.40
1.27
5.72
0°
0.10
0.19
5.80
0.25
8°
0.25
0.25
6.20
0.50
MAX
10.0
4.00
1.75
0.51
1.27
B
P
H
A
B
C
C
R x 45
1
G
8
D
F
G
-T-
D
0.25 (0.010) M T C M
K
SEATING
PLANE
J
F
M
H
J
K
M
P
R
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for
B - 0.25 mm (0.010) per side.
5
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