FSYC055D,
FSYC055R
July 1998
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFETs
Description
The Discrete Products Operation of Intersil has developed a
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity to Single Event Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with 100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space environ-
ments. The dose rate and neutron tolerance necessary for
military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regula-
tion, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
PART NO./BRAND
FSYC055D1
FSYC055D3
FSYC055R1
FSYC055R3
FSYC055R4
D
Features
• 70A (Note), 60V, r
DS(ON)
= 0.012
Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 6.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cmg
Ordering Information
RAD LEVEL
10K
10K
100K
100K
100K
SCREENING LEVEL
Commercial
TXV
Commercial
TXV
Space
Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil for any desired deviations
from the data sheet.
Symbol
Formerly available as type TA17650.
G
S
Packaging
SMD-2
NOTE:
Current limited by package capability.
©2001 Fairchild Semiconductor Corporation
FSYC055D, FSYC055R Rev. A
FSYC055D, FSYC055R
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSYC055D, FSYC055R
60
60
70 (Note)
56
200
±
20
162
65
1.30
200
70
200
-55 to 150
300
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20k
Ω
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Derated Above 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure). . . . . . . . . . . . . . . . . . . .I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: Current limited by package capability.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
60
-
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 12V
V
GS
= 0V to 2V
V
DD
= 30V,
I
D
= 70A
-
-
-
-
-
I
D
= 70A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.008
-
-
-
-
-
-
150
-
40
53
7
4750
2200
475
-
MAX
-
5.0
4.0
-
25
250
100
200
0.882
0.012
0.019
50
65
80
40
290
170
15
55
75
-
-
-
-
0.77
UNITS
V
V
V
V
µ
A
µ
A
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge at 12V
Threshold Gate Charge
Gate Charge Source
Gate Charge Drain
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(12)
Q
g(TH)
Q
gs
Q
gd
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= 48V,
V
GS
= 0V
V
GS
=
±
20V
V
GS
= 12V, I
D
= 70A
I
D
= 56A,
V
GS
= 12V
V
DD
= 30V, I
D
= 70A,
R
L
= 0.43
Ω
, V
GS
= 12V,
R
GS
= 2.35
Ω
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
©2001 Fairchild Semiconductor Corporation
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 70A
I
SD
= 70A, dI
SD
/dt = 100A/
µ
s
MIN
0.6
-
TYP
-
-
MAX
1.8
300
UNITS
V
ns
FSYC055D, FSYC055R Rev. A
FSYC055D, FSYC055R
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate-Body Leakage
Zero-Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 48V
V
GS
= 12V, I
D
= 70A
V
GS
= 12V, I
D
= 56A
MIN
60
1.5
-
-
-
-
MAX
-
4.0
100
25
0.882
0.012
UNITS
V
V
nA
µA
V
Ω
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
ION
SPECIES
Ni
Br
Br
Br
|
|
|
|
|
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm
2
(typical), T = 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
26
37
37
37
60
60
60
60
60
TYPICAL
RANGE (µ)
43
36
36
36
31
31
31
31
31
APPLIED
V
GS
BIAS
(V)
-20
-10
-15
-20
0
-5
-10
-15
-20
(NOTE 6)
MAXIMUM
V
DS
BIAS
(V)
60
60
48
36
60
48
36
24
12
TEST
Single Event Effects Safe Operating
Area
SYMBOL
SEESOA
Typical Performance Curves
1-
2-
3-
70
60
50
V
DS
(V)
40
30
20
10
TEMP = 25
o
C
0
0
-5
-10
V
GS
(V)
-15
-20
-25
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
2
3
1
LET = 26MeV/mg/cm
2
, RANGE = 43µ
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LET = 60MeV/mg/cm
2
, RANGE = 31µ
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
LIMITING INDUCTANCE (HENRY)
1E-3
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
©2001 Fairchild Semiconductor Corporation
FSYC055D, FSYC055R Rev. A
FSYC055D, FSYC055R
Typical Performance Curves
100
90
80
I
D
, DRAIN CURRENT (A)
70
I
D
, DRAIN (A)
60
50
40
30
20
10
0
-50
0
50
100
150
1
0.1
100
100µs
(Continued)
500
T
C
= 25
o
C
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10ms
T
C
, CASE TEMPERATURE (
o
C)
10
100
1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
500
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 56A
2.0
12V
Q
G
NORMALIZED r
DS(ON)
1.5
Q
GS
V
G
Q
GD
1.0
0.5
CHARGE
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
10
FIGURE 6. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
THERMAL RESPONSE (Z
θJC
)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
qJC
+ T
C
10
-3
10
-2
10
-1
P
DM
NORMALIZED
0.1
t
1
t
2
10
0
10
1
0.001
10
-5
10
-4
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
©2001 Fairchild Semiconductor Corporation
FSYC055D, FSYC055R Rev. A
FSYC055D, FSYC055R
Typical Performance Curves
500
(Continued)
I
AS
, AVALANCHE CURRENT (A)
STARTING T
J
= 25
o
C
100
STARTING T
J
= 150
o
C
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
10
0.01
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
10
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
50Ω
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
V
DD
t
ON
t
D(ON)
t
OFF
t
D(OFF)
t
R
t
F
90%
R
L
V
DS
V
GS
= 12V
DUT
0V
R
GS
V
DS
90%
10%
10%
90%
V
GS
10%
50%
PULSE WIDTH
50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSYC055D, FSYC055R Rev. A
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