Burr Brown Products
from Texas Instruments
ADS8370
SLAS450 – JUNE 2005
16-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE
FEATURES
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600-kHz Sample Rate
±0.5 LSB Typ, ±1.25 LSB Max INL
±0.4 LSB Typ, ±0.75 LSB Max DNL
16-Bit NMC
SINAD 89.5 dB, SFDR 119 dB at f
i
= 1 kHz
High-Speed Serial Interface up to 40 MHz
Onboard Reference Buffer
Onboard 4.096-V Reference
Pseudo-Differential Input, 0 V to 4.2 V
Onboard Conversion Clock
Selectable Output Format, 2's Complement or
Straight Binary
Zero Latency
Wide Digital Supply
Low Power:
– 110 mW at 600 kHz
– 15 mW During Nap Mode
– 10
µW
During Power Down
28-Pin 6 x 6 QFN Package
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Pin compatible With 18-Bit ADS8380
APPLICATIONS
Medical Instruments
Optical Networking
Transducer Interface
High Accuracy Data Acquisition Systems
Magnetometers
DESCRIPTION
The ADS8370 is a high performance 16-bit, 600-kHz
A/D converter with single-ended (pseudo-differential)
input. The device includes an 16-bit capacitor-based
SAR A/D converter with inherent sample and hold.
The ADS8370 offers a high-speed CMOS serial
interface with clock speeds up to 40 MHz.
The ADS8370 is available in a 28 lead 6 × 6 QFN
package and is characterized over the industrial
–40°C to 85°C temperature range.
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High Speed SAR Converter Family
Type/Speed
18-Bit Pseudo-Diff
18-Bit Pseudo-Bipolar, Fully Diff
16-Bit Pseudo-Diff
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
ADS7886
500 kHz
ADS8383
~ 600 kHz
ADS8381
ADS8380 (S)
ADS8382 (S)
ADS8370 (S)
ADS8372 (S)
ADS8371
ADS8401/05
ADS8402/06
ADS7890 (S)
ADS8411
ADS8412
ADS7891
ADS7881
750 kHZ
1 MHz
1.25 MHz
2 MHz
3 MHz
4 MHz
SAR
+IN
−IN
REFIN
4.096-V
Internal
Reference
+
_
CDAC
Comparator
Output
Latches
and
3-State
Drivers
FS
SCLK
SB/2C
SDO
REFOUT
Clock
Conversion
and
Control Logic
CS
CONVST
BUSY
PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
ADS8370
www.ti.com
SLAS450 – JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
Small Tape and
reel 250
Tape and reel
2500
Small Tape and
reel 250
Tape and reel
2500
ADS8370I
±2
–1/1.5
16
28 Pin
6×6 QFN
ADS8370IRHPT
RHP
–40°C to 85°C
ADS8370IRHPR
ADS8370IBRHPT
RHP
–40°C to 85°C
ADS8370IBRHPR
ADS8370IB
±1.25
±0.75
16
28 Pin
6×6 QFN
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
+IN to AGND
Voltage
–IN to AGND
+VA to AGND
+VBD to BDGND
Digital input voltage to BDGND
Digital input voltage to +VA
Operating free-air temperature range, T
A
Storage temperature range, T
stg
Junction temperature (T
J
max)
QFN package
Lead temperature, soldering
(1)
Power dissipation
θ
JA
thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
–0.3 V to +VA + 0.3 V
–0.3 V to +VA + 0.3 V
–0.3 V to 6 V
–0.3 V to 6 V
–0.3 V to +VBD + 0.3 V
+0.3 V
–40°C to 85°C
–65°C to 150°C
150°C
(T
J
max – T
A
)/θ
JA
86°C/W
215°C
220°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8370
www.ti.com
SLAS450 – JUNE 2005
SPECIFICATIONS
At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, f
SAMPLE
= 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down, see
Table 2.)
PARAMETER
ANALOG INPUT
Full-scale
input voltage
(1)
Absolute input voltage
Sampling capacitance
(measured from ±IN to
AGND)
Input leakage current
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
Integral linearity
(2) (3) (4)
Differential linearity
(3)
Offset error
(3)
TEST CONDITIONS
ADS8370IB
MIN
TYP
MAX
MIN
ADS8370I
TYP
MAX
UNIT
+IN – (–IN)
+IN
–IN
0
–0.2
–0.2
40
1
V
ref
V
ref
+ 0.2
0.2
0
–0.2
–0.2
40
1
V
ref
V
ref
+ 0.2
0.2
V
V
pF
nA
16
16
Quiet zones observed
Quiet zones not observed
Quiet zones observed
Quiet zones not observed
–0.75
–0.75
–1.25
±0.5
±0.8
±0.4
±0.75
±0.4
±0.4
–0.075
±1.25
At DC
80
55
40
55
0.075
–0.15
0.75
–1.5
0.75
–1
1.25
16
–2
16
Bits
Bits
2
LSB
(16 bit)
LSB
(16 bit)
mV
ppm/°C
0.15
%FS
ppm/°C
DNL
E
O
E
G
1.5
1.5
±0.4
Offset temperature drift
(3)
Gain error
(3) (5)
Gain temperature drift
(3) (5)
±1.25
80
55
40
55
CMRR
Common-mode rejection ratio
[+IN – (–IN)] = V
ref
/2 with
50 mV
p-p
common mode
signal at 1 MHz
At 0 V analog input
At full scale analog input
dB
Noise
PSRR
DC Power supply rejection
ratio
µV
RMS
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
Throughput rate
Aperture delay
Aperture jitter
Step response
Overvoltage recovery
(6)
1.0
0.50
1.16
1.0
0.50
1.16
µs
µs
kHz
ns
ps RMS
ns
ns
600
10
12
400
400
10
12
400
400
600
(1)
(2)
(3)
(4)
(5)
(6)
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Measured using analog input circuit in
Figure 51
and digital stimulus in
Figure 56
and
Figure 57
and reference voltage of 4.096 V.
This is endpoint INL, not best fit.
Measured using external reference source so does not include internal reference voltage error or drift.
Defined as sampling time necessary to settle an initial error of Vref on the sampling capacitor to a final error of 1 LSB at 16-bit level.
Measured using the input circuit in
Figure 51.
3
ADS8370
www.ti.com
SLAS450 – JUNE 2005
SPECIFICATIONS (continued)
At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, f
SAMPLE
= 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down, see
Table 2.)
PARAMETER
DYNAMIC CHARACTERISTICS
VIN = 4 V
p-p
at 1 kHz
THD
Total harmonic
distortion
(7) (8)
VIN = 4 V
p-p
at 10 kHz
VIN = 4 V
p-p
at 100 kHz
VIN = 4 V
p-p
at 1 kHz
SNR
Signal-to-noise
ratio
(7)
VIN = 4 V
p-p
at 10 kHz
VIN = 4 V
p-p
at 100 kHz
VIN = 4 V
p-p
at 1 kHz
SINAD
Signal-to-noise
+ distortion
(7) (8)
VIN = 4 V
p-p
at 10 kHz
VIN = 4 V
p-p
at 100 kHz
VIN = 4 V
p-p
at 1 kHz
SFDR
Spurious free dynamic
range
(7)
–3dB Small signal bandwidth
REFERENCE INPUT
V
ref
Reference voltage input range
Resistance
(9)
INTERNAL REFERENCE OUTPUT
V
ref
Reference voltage range
Source current
Line regulation
Drift
DIGITAL INPUT/OUTPUT
Logic family CMOS
V
IH
V
IL
V
OH
V
OL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
I
OH
= 2 TTL loads
I
OL
= 2 TTL loads
+VBD – 1
–0.3
+VBD –0.6
0.4
+VBD + 0.3
0.8
+VBD – 1
–0.3
+VBD –0.6
0.4
+VBD + 0.3
0.8
V
V
V
V
IOUT = 0 A, T
A
= 30°C
Static load
+VA = 4.75 V to 5.25 V
IOUT = 0 A
2.5
25
4.088
4.096
4.104
10
2.5
25
4.088
4.096
4.104
10
V
µA
mV
ppm/°C
2.5
4.096
10
4.2
2.5
4.096
10
4.2
V
MΩ
VIN = 4 V
p-p
at 10 kHz
VIN = 4 V
p-p
at 100 kHz
–112
–111
–92
89.5
89.5
89.5
89.5
89.5
87.5
119
117
92
75
–111
–111
–92
89.5
89
88.5
89.5
89
87
119
117
92
75
MHz
dB
dB
dB
dB
TEST CONDITIONS
ADS8370IB
MIN
TYP
MAX
MIN
ADS8370I
TYP
MAX
UNIT
Data format: MSB first, 2's complement or straight binary (selectable via the SB/2C pin)
POWER SUPPLY REQUIREMENTS
Power supply
voltage
I
CC
+VA
+VBD
+VA = 5 V
4.75
2.7
5
3.3
22
5.25
5.25
25
4.75
2.7
5
3.3
22
5.25
5.25
25
V
V
mA
Supply current, 600-kHz
sample rate
(10)
POWER DOWN
I
CC(PD)
I
CC(NAP)
Supply current, power down
2
2
µA
mA
300
ns
NAP MODE
Supply current, nap mode
Power-up time from nap
TEMPERATURE RANGE
Specified performance
–40
85
–40
85
°C
3
300
3
(7)
(8)
(9)
(10)
Measured using analog input circuit in
Figure 51
and digital stimulus in
Figure 56
and
Figure 57
and reference voltage of 4.096 V.
Calculated on the first nine harmonics of the input frequency.
Can vary +/-30%.
This includes only +VA current. With +VBD = 5 V, +VBD current is typically 1 mA with a 10-pF load capacitance on the digital output
pins.
4
ADS8370
www.ti.com
SLAS450 – JUNE 2005
TIMING REQUIREMENTS
(1) (2) (3) (4) (5) (6)
PARAMETER
t
conv
t
acq1
t
acq2
Conversion time
Acquisition time in normal mode
Acquisition time in nap mode (t
acq2
= t
acq1
+ t
d18
)
Quite sampling time (last toggle of interface signals to convert start
command)
(6)
Quite sampling time (convert start command to first toggle of interface
signals)
(6)
Quite conversion time (last toggle of interface signals to fall of BUSY)
(6)
Setup time, CONVST before BUSY fall
Setup time, CS before BUSY fall (only for conversion/sampling control)
Setup time, CONVST before CS rise (so CONVST can be recognized)
Hold time, CS after BUSY fall (only for conversion/sampling control)
Hold time, CONVST after CS rise
Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)
(4)
CONVST pulse duration
CS pulse duration
Pulse duration, time between conversion start command and conversion
abort command to successfully abort the ongoing conversion
SCLK period
SCLK duty cycle
t
su5
t
su6
t
su7
t
h5
t
h6
t
su2
t
su3
t
h2
t
h8
t
w2
t
w3
t
w4
Setup time, CS fall before first SCLK fall
Setup time, CS fall before FS rise
Setup time, FS fall before first SCLK fall
Hold time, CS fall after SCLK fall
Hold time, FS fall after SCLK fall
Setup time, CS fall before BUSY fall (only for read control)
Setup time, FS fall before BUSY fall (only for read control)
Hold time, CS fall after BUSY fall (only for read control)
Hold time, FS fall after BUSY fall (only for read control)
CS pulse duration
FS pulse duration
PD pulse duration for reset and power down
All unspecified pulse durations
(1)
(2)
(3)
(4)
(5)
(6)
25
40%
10
7
7
3
7
20
20
15
15
10
10
60
10
60%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
46,47
46,47
45
46,47
40,45
40,47
40,45
40,47
45
46,47
53,54
ADS8370I/ADS8370IB
MIN
1000
0.5
0.8
TYP
MAX
1160
UNIT
ns
µs
µs
REF
FIGURE
41 – 44
41,42,44
43
40 – 43,
45 – 47
40 – 43,
45 – 47
40 – 43,
45,47
41
40,41
41,43,44
41
43
42
43
41,42
44
CONVERSION AND SAMPLING
t
quiet1
t
quiet2
t
quiet3
t
su1
t
su2
t
su4
t
h1
t
h3
t
h4
t
w1
t
w2
t
w5
30
10
600
15
20
5
0
7
20
20
10
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA READ OPERATION
t
cyc
ns
45 – 47
MISCELLANEOUS
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
All digital output signals loaded with 10-pF capacitors.
CONVST_QUAL is CONVST latched by a low value on CS (see
Figure 39).
Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.
Quiet time zones are for meeting performance and not functionality.
5
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