STC
FEATURES
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Single CE Pin)
STC62WV51216
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.)
CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.)
CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The
STC62WV51216
is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of
1.5uA
at 3V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The
STC62WV51216
has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The
STC62WV51216
is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
2.4V ~ 5.5V
2.4V ~ 5.5V
SPEED
( ns )
55ns : 3.0~5.5V
70ns : 2.7~5.5V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
TSOP2-44
BGA-48-0912
TSOP2-44
BGA-48-0912
Vcc=3V
Vcc=5V
Vcc=3V
70ns
Vcc=5V
70ns
STC62WV51216EC
+0
O
C to +70
O
C
STC62WV51216FC
STC62WV51216EI
-40
O
C to +85
O
C
STC62WV51216FI
55 / 70
55 / 70
5uA
10uA
55uA
110uA
24mA
25mA
60mA
61mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
Vss
Vcc
DQ11
DQ10
DQ9
DQ8
A8
A9
A10
A11
A12
A13
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
STC62WV51216EC
STC62WV51216EI
4096
D0
16
Data
Input
Buffer
16
Column I/O
1
2
OE
UB
D10
D11
D12
D13
NC
.
A8
3
A0
A3
A5
A17
VSS
A 14
A12
A9
4
A1
A4
A6
A7
A16
A 15
A 13
A 10
5
A2
CE
D1
D3
D4
D5
WE
A 11
6
NC
D0
D2
V CC
V SS
D6
D7
NC
A
B
C
D
E
F
G
H
LB
D8
D9
V SS
V CC
D14
D15
A 18
.
.
.
.
D15
.
.
.
.
Write Driver
Sense Amp
256
Column Decoder
16
Data
Output
16
Buffer
CE
WE
OE
UB
LB
Vcc
Vss
Control
16
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
48-Ball CSP top View
STC International Limited
. reserves the right to modify document contents without notice.
R0201-STC62WV51216
1
Revision 2.1
Jan.
2004
STC
PIN DESCRIPTIONS
STC62WV51216
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
Name
A0-A18 Address Input
CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Vss
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
CE
H
X
L
L
L
WE
X
X
X
H
H
OE
X
X
X
H
L
LB
X
H
H
X
L
Read
H
L
L
Write
L
L
X
H
L
UB
X
H
H
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
UNITS
V
O
O
OPERATING RANGE
AMBIENT
RANGE
TEMPERATURE
Commercial
Industrial
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
C
DQ
V
I/O
=0V
12
pF
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not 100% tested.
maximum rating conditions for extended periods may affect reliability.
R0201-STC62WV51216
C
IN
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
10
2
Revision 2.1
Jan.
2004
STC
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(4)
STC62WV51216
TEST CONDITIONS
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
PARAMETER
Guaranteed Input Low
Voltage
(3)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
MIN. TYP.
-0.5
2.0
2.2
--
--
--
2.4
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(1)
MAX.
0.8
Vcc
+
0. 3
1
1
0.4
--
25
61
1
2
10
110
UNITS
V
V
uA
uA
V
V
mA
mA
uA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
,
or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE = V
IL
,I
DQ
= 0mA
,F = Fmax
(2)
CE = V
IH
,I
DQ
= 0mA
CE
≧
Vcc -0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
70ns
70ns
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current
-
TTL
Standby Current
-
CMOS
I
CCSB
I
CCSB1
(5)
1.5
8.0
1. Typical characteristics are at TA = 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc
_Max.
is 31mA(@3.0V) / 76mA(@5.0V) under 55ns operation.
5.I
cc
s
B1
is
5uA/55uA
at Vcc=3.0V/5.0V and T
A
=70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE
≧
Vcc - 0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.8
--
--
MAX.
--
2.5
--
--
UNITS
V
uA
ns
ns
2. t
RC
= Read Cycle Time
1. Vcc = 1.5V, T
A
= + 25
O
C
3. I
cc
DR
(Max.) is
1.3uA
at T
A
=70
O
C.
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
R0201-STC62WV51216
3
Revision 2.1
Jan.
2004
STC
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
STC62WV51216
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
(1)
CYCLE TIME : 70ns CYCLE TIME : 55ns
MIN. TYP. MAX.
Vcc = 2.7~5.5V
MIN. TYP. MAX.
Vcc = 3.0~5.5V
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
70
--
(CE)
(LB,UB)
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
55
--
--
--
--
10
5
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
--
--
30
30
25
--
--
--
--
10
5
5
--
--
--
10
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
(CE)
(LB,UB)
(CE)
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
Data Hold from Address Change
NOTE :
1. t
BA
is 35ns/30ns (@speed=70ns/55ns) with address toggle .
t
BA
is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-STC62WV51216
4
Revision 2.1
Jan.
2004
STC
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
STC62WV51216
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
ACS
t
BA
LB,UB
t
BE
D
OUT
t
(5)
CLZ
t
BDO
t
(5)
CHZ
READ CYCLE3
(1,4)
ADDRESS
t
RC
t
OE
AA
t
CE
OE
t
OH
t
t
t
(5)
CLZ
OLZ
ACS
t
t
OHZ
CHZ
(5)
(1,5)
LB,UB
t
BE
t
t
BA
BDO
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL .
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-STC62WV51216
5
Revision 2.1
Jan.
2004
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