5962-8992801XA datasheet, PDF - EEWORLD Datasheet

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5962-8992801XA: Description1280X1024 PIXELS PALETTE-DAC DSPL CTLR, CPGA84, CERAMIC, PGA-84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size495KB，26 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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5962-8992801XA Overview

1280X1024 PIXELS PALETTE-DAC DSPL CTLR, CPGA84, CERAMIC, PGA-84

5962-8992801XA Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Contains lead
Parts packaging code	PGA
package instruction	PGA,
Contacts	84
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	2
maximum clock frequency	110 MHz
show configuration	1280 X 1024 PIXELS
External data bus width	8
JESD-30 code	S-CPGA-P84
JESD-609 code	e0
length	32 mm
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	5.21 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	32 mm
uPs/uCs/peripheral integrated circuit type	DISPLAY CONTROLLER, PALETTE DAC
Base Number Matches	1

5962-8992801XA Related Products

	5962-8992801XA	TLC34058-110MGAB	5962-8992801XC
Description	1280X1024 PIXELS PALETTE-DAC DSPL CTLR, CPGA84, CERAMIC, PGA-84	1280X1024 PIXELS PALETTE-DAC DSPL CTLR, CPGA84, CERAMIC, PGA-84	1280X1024 PIXELS PALETTE-DAC DSPL CTLR, CPGA84, CERAMIC, PGA-84
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments
Is it lead-free?	Contains lead	Contains lead	Contains lead
Parts packaging code	PGA	PGA	PGA
package instruction	PGA,	PGA,	PGA,
Contacts	84	84	84
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.3	3A001.A.2.C
Address bus width	2	2	2
maximum clock frequency	110 MHz	110 MHz	110 MHz
show configuration	1280 X 1024 PIXELS	1280 X 1024 PIXELS	1280 X 1024 PIXELS
External data bus width	8	8	8
JESD-30 code	S-CPGA-P84	S-CPGA-P84	S-CPGA-P84
length	32 mm	32 mm	32 mm
Number of terminals	84	84	84
Maximum operating temperature	125 °C	70 °C	125 °C
Minimum operating temperature	-55 °C	-	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA	PGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.21 mm	5.21 mm	5.21 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	COMMERCIAL	MILITARY
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	32 mm	32 mm	32 mm
uPs/uCs/peripheral integrated circuit type	DISPLAY CONTROLLER, PALETTE DAC	DISPLAY CONTROLLER, PALETTE DAC	DISPLAY CONTROLLER, PALETTE DAC
Base Number Matches	1	1	-

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