PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and
reset
Rev. 6 — 6 February 2013
Product data sheet
1. General description
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion with interrupt and reset for I
2
C-bus/SMBus applications
and was developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders.
I/O expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push-buttons, LEDs, fans, etc.
The PCA9538 consists of an 8-bit Configuration register (input or output selection),
8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the Input
Port register can be inverted with the Polarity Inversion register. All registers can be read
by the system master.
The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O
pull-up resistor which greatly reduces power consumption when the I/Os are held LOW,
replacement of A2 with RESET and different address range.
The PCA9538 open-drain interrupt output (INT) is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed. The power-on reset sets the registers to their
default values and initializes the device state machine. The RESET pin causes the same
reset/initialization to occur without de-powering the device.
Two hardware pins (A0 and A1) vary the fixed I
2
C-bus address and allow up to four
devices to share the same I
2
C-bus/SMBus.
2. Features and benefits
8-bit I
2
C-bus GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V to 5.5 V
(5.0 V
10 % for PCA9538PW/Q900 AEC-Q100 compliant devices)
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Active LOW reset input
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Internal power-on reset
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Offered in three different packages: SO16, TSSOP16 and HVQFN16
3. Ordering information
Table 1.
Ordering information
Topside
marking
9538
PCA9538D
PCA9538
PCA9538
Package
Name
HVQFN16
SO16
TSSOP16
TSSOP16
Description
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
4
0.85 mm
plastic small outline package; 16 leads;
body width 7.5 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT629-1
SOT162-1
SOT403-1
SOT403-1
Type number
PCA9538BS
PCA9538D
PCA9538PW
PCA9538PW/Q900
[1]
[1]
PCA9538PW/Q900 is AEC-Q100 compliant. Contact
i2c.support@nxp.com
for PPAP.
3.1 Ordering options
Table 2.
Ordering options
Orderable part number Package
Packing method
Minimum Temperature
order
quantity
6000
1920
1000
2400
2500
2500
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
Type number
PCA9538BS
PCA9538D
PCA9538BS,118
PCA9538D,112
PCA9538D,118
HVQFN16
SO16
SO16
TSSOP16
TSSOP16
TSSOP16
Reel pack, SMD,
13-inch
Tube, bulk pack
Reel pack, SMD,
13-inch
Tube, bulk pack
Reel pack, SMD,
13-inch
Reel pack, SMD,
13-inch
PCA9538PW
PCA9538PW,112
PCA9538PW,118
PCA9538PW/Q900
PCA9538PW/Q900,118
PCA9538
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
2 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
4. Block diagram
A0
A1
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
8-bit
INPUT/
OUTPUT
PORTS
write pulse
read pulse
V
DD
RESET
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
DD
POWER-ON
RESET
V
SS
PCA9538
LP
FILTER
002aae667
INT
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9538
PCA9538
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
3 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
A0
A1
RESET
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aae668
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
A0
A1
RESET
IO0
IO1
IO2
IO3
V
SS
1
2
3
4
5
6
7
8
002aae669
16 V
DD
15 SDA
14 SCL
13 INT
12 IO7
11 IO6
10 IO5
9
IO4
PCA9538D
PCA9538PW
PCA9538PW/Q900
Fig 2.
Pin configuration for SO16
16 A1
15 A0
terminal 1
index area
Fig 3.
13 SDA
14 V
DD
Pin configuration for TSSOP16
RESET
IO0
IO1
IO2
1
2
12 SCL
11 INT
PCA9538BS
3
4
5
6
7
8
10 IO7
9
IO6
V
SS
IO3
IO4
IO5
002aae670
Transparent top view
Fig 4.
Pin configuration for HVQFN16
PCA9538
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
4 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
Table 3.
Symbol
A0
A1
RESET
IO0
IO1
IO2
IO3
V
SS
IO4
IO5
IO6
IO7
INT
SCL
SDA
V
DD
[1]
Pin description
Pin
SO16, TSSOP16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVQFN16
15
16
1
2
3
4
5
6
[1]
7
8
9
10
11
12
13
14
address input 0
address input 1
active LOW reset input
input/output 0
input/output 1
input/output 2
input/output 3
supply ground
input/output 4
input/output 5
input/output 6
input/output 7
interrupt output (open-drain)
serial clock line
serial data line
supply voltage
Description
HVQFN16 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
PCA9538
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
5 of 34
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