IDT7052L20PFG datasheet, PDF - EEWORLD Datasheet

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IDT7052L20PFG: DescriptionFour-Port SRAM, 2KX8, 20ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-120; Categorystorage storage; File Size73KB，6 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT7052L20PFG Overview

Four-Port SRAM, 2KX8, 20ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-120

IDT7052L20PFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LFQFP, QFP120,.63SQ,16
Contacts	120
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	20 ns
Other features	AUTOMATIC POWER-DOWN
I/O type	COMMON
JESD-30 code	S-PQFP-G120
JESD-609 code	e3
length	14 mm
memory density	16384 bit
Memory IC Type	FOUR-PORT SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of ports	4
Number of terminals	120
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP120,.63SQ,16
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.0006 A
Minimum standby current	2 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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USING THE IDT7052/7054

FOURPORT™ SRAMs

IN DSP AND MATRIX

PROCESSING APPLICATIONS

By Tao Lin, Julie Lin, and Yupling Chung

APPLICATION

NOTE

AN-42

Introduction

Most digital signal processing (DSP) algorithms have inherent par-

allelism and may be pipelined. Usually, these algorithms are computa-

tion intensive. In real-time applications, multiprocessor or parallel dis-

tributed processor systems are commonly used to implement these

DSP algorithms. In these types of systems it is necessary for different

processors to randomly and independently access different locations at

the same time in the same memory space. The IDT7052 (2Kx8) and

IDT7054 (4Kx8) FourPort RAMs are powerful devices to efficiently

and compactly implement the memory space in these applications. More-

over, the IDT7052 and IDT7054 can increase the speed of these

types of systems since the FourPort SRAMs are as fast as conven-

tional SRAMs and eliminate the complex external logic which intro-

duces extra delay in these systems. In this application note, we will

demonstrate some examples of using the IDT7052 to implement a high

performance FFT processor and a matrix multiplication engine.

G = C + e jΩ • D

H = C - e jΩ • D

Figure 1. The signal flow graph of the butterfly

2684 drw 01

e jΩ

Using the IDT7052 in an FFT

Processor

The IDT7052 FourPort SRAM can dramatically simplify the design

of a high-speed pipelined FFT processor. The basic operation of any

FFT algorithm is the butterfly computation:

G = C + e

H=C-e

x(0)

x(1)

x(2)

x(3)

x(4)

x(5)

x(6)

x(7)

Stage 1

• D

(1-1)

• D

where C, D, G, and H are complex numbers. Figure 1 shows the

signal flow graph of the butterfly with one complex multiplication and

two complex additions. Given N = 2

input data samples x(0), x(1).....,

x(N-1), the FFT algorithm performs the Discrete Fourier Transform on

the input data to obtain the output data X(0), X(1)....., X(N-1) in L

stages of computation. Each stage consists of N/2 butterfly operations.

There are two basic versions of the FFT algorithm: decimation-in-time

(DIT) and decimation-in-frequency (DIF). Each version of the algo-

rithm can be implemented using two schemes: not-in-place computation

and in-place computation. A detailed discussion of the FFT algorithm

and its implementations is given in Reference (1).

Figure 2 shows the signal flow graph of the not-in-place computa-

tion of the DIT FFT algorithm for N = 8(L=3). A close look at Figure 2

will reveal the major strength of the not-in-place scheme. The signal

X(0)

X(4)

X(2)

X(6)

X(1)

X(5)

X(3)

X(7)

Stage 2

Stage 3

2684 drw 02

-j2πk/N

Figure 2. Signal Flow Graph of Not-In-Place Decimation-In-Time FFT for N=8

MARCH 2000

6.01

2684/2

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