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71V30S35TFGI

Description
Dual-Port SRAM, 1KX8, 35ns, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, GREEN, STQFP-64
Categorystorage    storage   
File Size121KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

71V30S35TFGI Overview

Dual-Port SRAM, 1KX8, 35ns, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, GREEN, STQFP-64

71V30S35TFGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction10 X 10 MM, 1.40 MM HEIGHT, GREEN, STQFP-64
Contacts64
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
JESD-30 codeS-PQFP-F64
JESD-609 codee3
memory density8192 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals64
word count1024 words
character code1000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX8
Package body materialPLASTIC/EPOXY
encapsulated codeQFF
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formFLAT
Terminal locationQUAD
Maximum time at peak reflow temperature30
Base Number Matches1
HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
IDT71V30S/L
High-speed access
– Commercial: 25/35/55ns (max.)
Low-power operation
– IDT71V30S
Active: 375mW (typ.)
Standby: 5mW (typ.)
– IDT71V30L
Active: 375mW (typ.)
Standby: 1mW (typ.)
On-chip port arbitration logic
Interrupt flags for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40
O
C to +85
O
C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/
W
L
OE
R
CE
R
R/
W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
(1)
A
9L
A
0L
Address
Decoder
10
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3741 drw 01
(2)
NOTES:
1. IDT71V30:
BUSY
outputs are non-tristatable push-pulls.
2.
INT
outputs are non-tristable push-pull output structure.
NOVEMBER 2009
1
©2009 Integrated Device Technology, Inc.
DSC 3741/10
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