The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFO™ is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
register in either direction.
The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed, submicron CMOS
technology.
Two independent FIFO memories for fully bidirectional data
transfers
256 x 18 x 2 organization (IDT72605)
512 x 18 x 2 organization (IDT72615)
Synchronous interface for fast (20ns) read and write cycle times
Each data port has an independent clock and read/write control
Output enable is provided on each port as a three-state control
of the data bus
Built-in bypass path for direct data transfer between two ports
Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
Programmable flag offset can be set to any depth in the FIFO
The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
°
°
Industrial temperature range (–40°C to +85°C)
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D
A0
-D
A17
EN
A
R/W
A
OE
A
HIGH
Z
CONTROL
CLK
A
INPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
MUX
MEMORY
ARRAY
512 x 18
256 x 18
RESET
LOGIC
RS
CS
A
A
2
A
1
A
0
EF
AB
PAE
AB
PAF
AB
FF
AB
µP
INTERFACE
FLAG
LOGIC
FLAG
LOGIC
EF
BA
PAE
BA
PAF
BA
FF
BA
3
7
POWER
SUPPLY
INPUT REGISTER
V
CC
GND
CLK
B
HIGH
Z
CONTROL
OUTPUT REGISTER
OE
B
R/W
B
EN
B
BYP
B
D
B0
-D
B17
2704 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
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Robotics Development
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