Preliminary
K6F1616U6M Family
Document Title
1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
0.1
Initial draft
Revise
- Change package type : from FBGA to TBGA
Draft Date
August 22, 2000
November 21, 2000
Remark
Preliminary
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 0.1
November 2000
Preliminary
K6F1616U6M Family
FEATURES
•
Process Technology: Full CMOS
•
Organization: 1M x16
•
Power Supply Voltage: 2.7~3.3V
•
Low Data Retention Voltage: 1.5V(Min)
•
Three state output
•
Package Type: 48-TBGA-9.00x12.00
CMOS SRAM
GENERAL DESCRIPTION
The K6F1616U6M families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRO
DUCT FAMILY
Power Dissipation
Product Family
K6F1616U6M-F
Operating Temperature
Industrial(-40~85°C)
Vcc Range
2.7~3.3V
Speed
55
1)
/70ns
Standby
(I
SB1
, Typ.)
2µA
Operating
(I
CC1
, Max)
4mA
PKG Type
48-TBGA-9.00x12.00
1. The parameter is measured with 30pF test load.
2. Typical value are measured at V
CC
=3.0V, T
A
=25°C and not 100% tested.
PIN DESCRIPTION
1
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A
LB
OE
A0
A1
A2
CS2
Vcc
Vss
B
I/O9
UB
A3
A4
CS1
I/O1
Row
Addresses
C
Row
select
I/O10
I/O11
A5
A6
I/O2
I/O3
Memory
Cell
Array
D
Vss
I/O12
A17
A7
I/O4
Vcc
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
E
Vcc
I/O13
Vss
A16
I/O5
Vss
I/O
1
~I/O
8
F
I/O
9
~I/O
16
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
A19
A12
A13
WE
I/O8
Column Addresses
H
A18
A8
A9
A10
A11
DNU
CS1
48-TBGA: Top View (Ball Down)
CS2
OE
WE
Control Logic
Name
CS
1
, CS
2
OE
WE
A
0
~A
19
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Name
Vcc
Vss
UB
LB
DNU
Function
Power
Ground
Upper Byte(I/O
9
~
16
)
Lower Byte(I/O
1
~
8
)
Do Not Use
UB
LB
I/O
1
~I/O
16
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 0.1
November 2000
Preliminary
K6F1616U6M Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F1616U6M-EF55
K6F1616U6M-EF70
Function
48-TBGA, 55ns, 3.0V
48-TBGA, 70ns, 3.0V
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
X
1)
L
L
L
L
L
L
L
L
CS
2
X
1)
L
X
1)
H
H
H
H
H
H
H
H
OE
X
1)
X
1)
X
1)
H
H
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
X
1)
X
1)
H
H
H
H
H
L
L
L
LB
X
1)
X
1)
H
L
X
1)
L
H
L
L
H
L
UB
X
1)
X
1)
H
X
1)
L
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to V
CC
+0.3V(Max. 3.6V)
-0.2 to 3.6
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 0.1
November 2000
Preliminary
K6F1616U6M Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.0
0
-
-
CMOS SRAM
Max
3.3
0
Vcc+0.2
2)
0.6
Unit
V
V
V
V
Note:
1. T
A
=-40 to 85°C, otherwise specified
2. Overshoot: V
CC
+2.0V in case of pulse width
≤20ns.
3. Undershoot: -2.0V in case of pulse width
≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Symbol
Test Conditions
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
,
V
IO
=Vss to Vcc
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
LB≤0.2V
or/and UB≤0.2V, CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty, CS
1
=V
IL
,
CS
2
=V
IH
, LB=V
IL
or/and UB=V
IL
, V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
Other input =0~Vcc
1) CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or
2) 0V≤CS
2
≤0.2V(CS
2
controlled) or
3) LB=UB≥Vcc-0.2V, CS
2
≥Vcc-0.2V(LB/UB
controlled)
70ns
55ns
Min
-1
-1
-
-
-
-
2.4
Typ
1)
-
-
-
-
-
-
-
Max
1
1
4
35
40
0.4
-
Unit
µA
µA
mA
mA
V
V
µA
I
LI
I
LO
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
V
OL
V
OH
Standby Current (CMOS)
I
SB1
-
2.0
40
1. Typical value are measured at V
CC
=3.0V, T
A
=25°C and not 100% tested.
4
Revision 0.1
November 2000
Preliminary
K6F1616U6M Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
LB, UB valid to data output
Read
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
BA
t
LZ1
, t
LZ2
t
OLZ
t
BLZ
t
OH
t
HZ1
, t
HZ2
t
OHZ
t
BHZ
t
WC
t
CW1
, t
CW2
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
BW
55
-
-
-
-
10
5
10
10
0
0
0
55
45
0
45
40
0
0
25
0
5
45
55ns
Max
-
55
55
25
55
-
-
-
-
20
20
20
-
-
-
-
-
-
20
-
-
-
-
Min
70
-
-
-
-
10
5
10
10
0
0
0
70
60
0
60
50
0
0
30
0
5
60
70ns
Max
-
70
70
35
70
-
-
-
-
25
25
25
-
-
-
-
-
-
20
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CS
1
≥Vcc-0.2V
1)
, V
IN
≥0V
Vcc=1.5V, CS
1
≥Vcc-0.2V
1)
, V
IN
≥0V
See data retention waveform
Min
1.5
-
0
tRC
Typ
-
1.0
2)
-
-
Max
3.3
15
-
-
Unit
V
µA
ns
1. 1) CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or
2) 0≤CS
2
≤0.2V(CS
2
controlled) or
3) LB=UB≥Vcc-0.2V, CS
2
≥Vcc-0.2V(LB/UB
controlled)
2. Typical value are measured at T
A
=25°C and not 100% tested.
5
Revision 0.1
November 2000
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