SCD128410QCE datasheet, PDF - EEWORLD Datasheet

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SCD128410QCE: DescriptionIEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports; CategoryThe embedded processor and controller Microcontrollers and processors; File Size962KB，176 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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SCD128410QCE Overview

IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

SCD128410QCE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	QFP, QFP100,.7X.9
Contacts	100
Reach Compliance Code	unknow
ECCN code	EAR99
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
Number of I/O lines	16
Number of ports	2
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.7X.9
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum slew rate	60 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, PRINTER INTERFACE
Base Number Matches	1

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CD1284

IEEE 1284-Compatible Parallel Interface Controller

with Two High-Speed Asynchronous Serial Ports

Datasheet

Product Features

Parallel Port (Peripheral-side)

High-speed, bidirectional, multi-protocol

parallel port:

Hardware implementation of all modes of

the IEEE STD (Standard) 1284

specification (including automatic

negotiation)

— Centronics



-compatible mode

— Reverse Byte mode

— Reverse Nibble mode

— ECP (extended capabilities port) mode

with run-length encoding/decoding

— EPP (enhanced parallel port) mode

— Up to 2-Mbytes/sec. transfer rate in ECP

and EPP modes

64-byte parallel FIFO with DMA interface

Two Serial UARTs

Serial channel asynchronous protocol

support to 115.2 kbps (register-set-

compatible and functionally identical to

CD1400)

— Twelve-byte FIFOs for each transmitter

and receiver with programmable

threshold for receive FIFO interrupt

generation

— Improved interrupt schemes: Good

Data



interrupts eliminate the need for

character status check

— User-programmable and automatic flow

control for serial channels

— Special character recognition and

generation.

— Special character processing,

particularly useful for UNIX



environments, optionally handled

automatically by the serial channels.

— Six modem control signals per channel

(DTR, DSR, RTS, CTS, CD, and RI)

As of May 2001, this document replaces the Basis

Communications Corp. document.

CL-CD1284 — IEEE 1284-Compatible Parallel Interface Controller

May 2001

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Contents

1.0

2.0

Overview

......................................................................................................................12

Conventions

...............................................................................................................15

2.1

2.2

Abbreviations.......................................................................................................15

Acronyms ............................................................................................................15

Pin Diagram.........................................................................................................17

Pin List.................................................................................................................18

Device Architecture .............................................................................................31

CPU Interface......................................................................................................33

5.2.1 Read Cycles ...........................................................................................33

5.2.2 Write Cycles ...........................................................................................34

5.2.3 Service-Acknowledge Cycles .................................................................34

5.2.4 DMA Cycles............................................................................................34

Serial Port Service Requests ..............................................................................35

5.3.1 Interrupts ................................................................................................36

5.3.2 DMAREQ* as Parallel Interrupt Source..................................................36

5.3.3 Serial Service Request Polling ...............................................................40

5.3.4 Daisy-Chaining Service Requests with CD1400s ..................................41

Parallel Port Service Requests............................................................................43

5.4.1 Hardware-Activated Context Switch, Parallel.........................................48

5.4.2 Software-Activated Context Switch, Parallel ..........................................49

Serial Data Reception and Transmission ............................................................49

5.5.1 Receiver Operation ................................................................................50

5.5.2 Receiver Timer Operations ....................................................................51

5.5.3 Receive Exceptions................................................................................52

5.5.4 Transmitter Operation ............................................................................54

Flow Control ........................................................................................................55

5.6.1 In-Band Flow Control..............................................................................55

5.6.2 Receiver In-Band Flow Control ..............................................................55

5.6.3 Out-of-Band Flow Control.......................................................................58

5.6.4 Modem Signals and General-Purpose I/O .............................................59

Receive Special Character Processing ...............................................................61

5.7.1 UNIX‚ Character Processing ..................................................................61

5.7.2 Non-UNIX‚ Receive Special Character Processing................................63

Transmit Special Character Processing ..............................................................67

5.8.1 Line Terminating Characters ..................................................................67

5.8.2 Embedded Transmit Commands............................................................67

5.8.3 Send Special Character Command........................................................68

Baud Rate Generation.........................................................................................72

3.0

Pin Information

..........................................................................................................17

3.1

3.2

4.0

...................................................................................................24

4.1

4.2

5.0

Functional Description

...........................................................................................31

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

Datasheet

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

5.10

5.11

5.12

5.13

5.14

5.15

5.16

5.17

Serial Diagnostic Facilities — Loopback ............................................................. 73

Parallel Port FIFO and Data Pipeline Overview .................................................. 73

5.11.1 IEEE STD 1284 Protocols ...................................................................... 73

5.11.2 Bus Interface .......................................................................................... 74

5.11.3 Parallel Port FIFO .................................................................................. 74

5.11.4 Receive Direction ................................................................................... 75

5.11.5 Receiving Compressed Data.................................................................. 75

5.11.6 Stale Data (Stale, OneChar, and Timeout Status Bits) .......................... 76

5.11.7 Transmit Direction .................................................................................. 76

CD1284 Parallel Port Overview .......................................................................... 77

5.12.1 Terminology ........................................................................................... 77

5.12.2 Signal Names ......................................................................................... 77

5.12.3 State Machine ........................................................................................ 78

5.12.4 Configuration.......................................................................................... 78

5.12.5 Interrupts ................................................................................................ 79

5.12.6 Manual Mode ......................................................................................... 79

5.12.7 Control Signals....................................................................................... 79

5.12.8 Parallel Port Interface to the FIFO ......................................................... 80

5.12.9 1284 Negotiations .................................................................................. 80

5.12.10 Data Transfers ....................................................................................... 81

5.12.11 Compatible Mode Status ........................................................................ 81

1284 Parallel Protocol Support ........................................................................... 82

5.13.1 Compatibility Mode................................................................................. 82

5.13.2 Reverse-Nibble and Reverse-Byte Modes ............................................. 82

5.13.3 ID Request ............................................................................................. 82

5.13.4 ECP Mode.............................................................................................. 82

5.13.5 EPP Mode .............................................................................................. 83

Protocol Timing ................................................................................................... 83

General-Purpose I/O Port ................................................................................... 83

Parallel Port Interface.......................................................................................... 84

Hardware Configurations .................................................................................... 86

5.17.1 Interfacing to an Intel‚ Microprocessor-Based System ........................... 86

5.17.2 Interfacing to a Motorola‚ Microprocessor-Based System...................... 86

5.17.3 Interfacing to a National Semiconductor‚

Microprocessor-Based System86

Overview ............................................................................................................. 90

Initialization ......................................................................................................... 90

6.2.1 Device Reset.......................................................................................... 90

6.2.2 Global Function Initialization .................................................................. 93

6.2.3 Serial Channel Initialization.................................................................... 93

Serial Poll Mode Examples ................................................................................. 94

6.3.1 Polling Routine Examples ...................................................................... 94

Hardware-Activated Service Examples............................................................... 97

6.4.1 Serial Receive Service ........................................................................... 97

6.4.2 Serial Transmit Service .......................................................................... 98

6.4.3 Modem Service ...................................................................................... 99

Parallel Channel Service Routines...................................................................... 99

6.5.1 Software-Activated Service Examples (Poll) ........................................ 100

6.0

Programming

............................................................................................................. 90

6.1

6.2

6.3

6.4

6.5

Datasheet

IEEE 1284-Compatible Parallel Interface Controller — CD1284

6.6

6.7

6.8

6.5.2 Hardware-Activated Service Examples ................................................102

Baud Rate Derivation ........................................................................................102

Baud Rate Tables..............................................................................................103

ASCII Code Tables............................................................................................106

6.8.1 Hexadecimal — Character ...................................................................106

6.8.2 Decimal — Character ...........................................................................107

Global Registers................................................................................................108

7.1.1 Channel Access Register .....................................................................108

7.1.2 Global Firmware Revision Code Register ............................................108

7.1.3 General-Purpose I/O Direction Register...............................................109

7.1.4 General-Purpose I/O Register..............................................................109

7.1.5 Modem Interrupting Channel Register .................................................109

7.1.6 Modem Interrupt Register.....................................................................110

7.1.7 Parallel Interrupt Register.....................................................................111

7.1.8 Prescaler Period Register ....................................................................111

7.1.9 Receive Interrupting Channel Register ................................................112

7.1.10 Receive Interrupt Register....................................................................112

7.1.11 Service Request Register.....................................................................112

7.1.12 Transmit Interrupting Channel Register ...............................................113

7.1.13 Transmit Interrupt Register...................................................................113

Virtual Registers ................................................................................................113

7.2.1 Modem Interrupt Status Register .........................................................114

7.2.2 Modem Interrupt Vector Register .........................................................114

7.2.3 Parallel Interrupt Vector Register .........................................................115

7.2.4 Receive Data/Status Registers ............................................................115

7.2.5 Receive Interrupt Vector Register ........................................................116

7.2.6 Transmit Data Register ........................................................................117

7.2.7 Transmit Interrupt Vector Register .......................................................117

7.2.8 End of Service Request Register .........................................................118

Channel Registers.............................................................................................118

7.3.1 Channel Command Register ................................................................118

7.3.2 Channel Control Status Register..........................................................122

Channel Registers — Parallel Pipeline .............................................................123

7.4.1 Channel Option Register 1 ...................................................................123

7.4.2 Channel Option Register 2 ...................................................................124

7.4.3 Channel Option Register 3 ...................................................................125

7.4.4 Channel Option Register 4 ...................................................................126

7.4.5 Channel Option Register 5 ...................................................................128

7.4.6 Local Interrupt Vector Register.............................................................128

7.4.7 LNext Character Register.....................................................................129

Modem Change Option Registers .....................................................................129

7.5.1 Modem Change Option Register 1.......................................................129

7.5.2 Modem Change Option Register 2.......................................................130

7.5.3 Modem Signal Value Register 1...........................................................130

7.5.4 Modem Signal Value Register 2...........................................................131

7.5.5 Receive Baud Rate Period Register.....................................................131

7.5.6 Receive Clock Option Register ............................................................131

7.5.7 Received Data Count Register .............................................................132

7.0

Detailed Register Descriptions

.........................................................................108

7.1

7.2

7.3

7.4

7.5

Datasheet

SCD128410QCE Related Products

	SCD128410QCE	CD1284	SCD1284
Description	IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports	IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports	IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

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