935281425125 datasheet, PDF - EEWORLD Datasheet

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935281425125: DescriptionAUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PQCC8, 1.6 X 1.6 MM, 0.5 MM HEIGHT, MO-255, SOT902-1, QFN-8U; Categorylogic logic; File Size276KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935281425125 Overview

AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PQCC8, 1.6 X 1.6 MM, 0.5 MM HEIGHT, MO-255, SOT902-1, QFN-8U

935281425125 Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	VQCCN,
Reach Compliance Code	unknown
series	AUP/ULP/V
JESD-30 code	S-PQCC-N8
length	1.6 mm
Logic integrated circuit type	AND GATE
Number of functions	2
Number of entries	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
propagation delay (tpd)	24 ns
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal pitch	0.55 mm
Terminal location	QUAD
width	1.6 mm
Base Number Matches	1

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74AUP2G08

Low-power dual 2-input AND gate

Rev. 7 — 18 January 2013

Product data sheet

1. General description

The 74AUP2G08 provides the dual 2-input AND function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1 000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

935281425125 Related Products

	935281425125	935292219115	74AUP2G08GF	74AUP2G08GN	74AUP2G08GS	935291475115
Description	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PQCC8, 1.6 X 1.6 MM, 0.5 MM HEIGHT, MO-255, SOT902-1, QFN-8U	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PDSO8, 1.2 X 1 MM, 0.35 MM HEIGHT, SOT1116, SON-8	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PDSO8, 1.35 X 1 MM, 0.5 MM HEIGHT, MO-252, SOT1089, SON-8	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PDSO8, 1.2 X 1 MM, 0.35 MM HEIGHT, SOT1116, SON-8	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PDSO8, 1.35 X 1 MM, 0.5 MM HEIGHT, SOT1203, SON-8	AUP/ULP/V SERIES, DUAL 2-INPUT AND GATE, PDSO8, 1.35 X 1 MM, 0.5 MM HEIGHT, MO-252, SOT1089, SON-8
package instruction	VQCCN,	SON,	1.35 X 1 MM, 0.5 MM HEIGHT, MO-252, SOT1089, SON-8	1.2 X 1 MM, 0.35 MM HEIGHT, SOT1116, SON-8	1.35 X 1 MM, 0.5 MM HEIGHT, SOT1203, SON-8	VSON,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	S-PQCC-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8
length	1.6 mm	1.2 mm	1.35 mm	1.2 mm	1.35 mm	1.35 mm
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
Number of functions	2	2	2	2	2	2
Number of entries	2	2	2	2	2	2
Number of terminals	8	8	8	8	8	8
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VQCCN	SON	VSON	SON	VSON	VSON
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	24 ns	24 ns	24 ns	24 ns	24 ns	24 ns
Maximum seat height	0.5 mm	0.35 mm	0.5 mm	0.35 mm	0.35 mm	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES	YES	YES
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.55 mm	0.3 mm	0.5 mm	0.3 mm	0.35 mm	0.5 mm
Terminal location	QUAD	DUAL	DUAL	DUAL	DUAL	DUAL
width	1.6 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Maker	NXP	NXP	NXP	NXP	NXP	-
JESD-609 code	-	e3	e3	e3	e3	e3
Terminal surface	-	TIN	TIN	PURE TIN	TIN	TIN

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