PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844246
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER W
/I
NTEGRATED
F
ANOUT
B
UFFER
F
EATURES
•
Six LVDS outputs
•
Crystal oscillator interface
•
Output frequency range: 53.125MHz to 333.3333MHz
•
Crystal input frequency range: 25MHz to 33.333MHz
•
RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.39ps (typical)
•
Full 3.3V or 3.3V core, 2.5V output supply mode
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free RoHS-compliant
packages
Function
G
ENERAL
D
ESCRIPTION
The ICS844246 is a Crystal-to-LVDS Clock
Synthesizer/Fanout Buffer designed for Fibre
HiPerClockS™
Channel and Gigabit Ethernet applications and
is a member of the HiperClockS™ family of
High Performance Clock Solutions from ICS.
The output frequency can be set using the frequency
select pins and a 25MHz crystal for Ethernet fre-
quencies, or a 26.5625MHz crystal for a Fibre Channel.
The low phase noise characteristics of the ICS844246
make it an ideal clock for these demanding applications.
IC
S
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_SEL
0
0
0
0
1
1
1
1
N_SEL1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
M Divide
20
20
20
20
24
24
24
24
N Divide
2
4
5
8
3
4
6
12
M/N
10
5
4
2.5
8
6
4
2
B
LOCK
D
IAGRAM
Q0
nQ0
PLL_BYPASS
Pullup
P
IN
A
SSIGNMENT
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
GND
GND
N_SEL0
XTAL_OUT
XTAL_IN
Q1
1
XTAL_IN
XTAL_OUT
nQ1
OSC
PLL
0
Output
Divider
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Feedback
Divider
FB_SEL
N_SEL1
N_SEL0
Pulldown
Pullup
Pullup
ICS843246
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm
body package
M Package
Top View
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
body package
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844246AM
www.icst.com/products/hiperclocks.html
1
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844246
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER W
/I
NTEGRATED
F
ANOUT
B
UFFER
Type
Power
Output
Output
Output
Input
Power
Power
Input
Input
Input
Pullup
Description
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Selects between the PLL and cr ystal inputs as the input to the dividers.
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Output
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9
10
11
12
13,
14
15,
18
16, 17
19, 20
21, 22
23, 24
Name
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
XTAL_IN,
XTAL_OUT
N_SEL0
N_SEL1
GND
nQ5, Q5
nQ4, Q4
nQ3, Q3
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
844246AM
www.icst.com/products/hiperclocks.html
2
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844246
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER W
/I
NTEGRATED
F
ANOUT
B
UFFER
Function
C
RYSTAL
F
UNCTION
T
ABLE
Inputs
XTAL (MHz)
25
25
25
25
25
25
25
25
26.5625
26.5625
26.5625
26.5625
26.5625
30
30
30
30
31.25
31.25
31.25
31.25
33.3333
33.3333
33.3333
33.3333
FB_SEL
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
N_SEL1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
M
20
20
20
20
24
24
24
24
20
24
24
24
24
20
20
20
20
20
20
20
20
20
20
20
20
500
500
500
500
600
600
600
600
531.25
637.5
637.5
637.5
637.5
600
600
600
600
625
62 5
62 5
625
666.6667
666.6667
666.6667
666.6667
VCO (MHz)
N
2
4
5
8
3
4
6
12
5
3
4
6
12
2
4
5
8
2
4
5
8
2
4
5
8
Output (MHz)
250
125
100
62.5
200
150
100
50
106.25
212.5
159.375
106.25
53.125
300
150
12 0
75
312.5
156.25
125
78.125
333.3333
166.6667
133.3333
83.3333
844246AM
www.icst.com/products/hiperclocks.html
3
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844246
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER W
/I
NTEGRATED
F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
50°C/W (0 lfpm)
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
24 Lead SOIC
24 Lead TSSOP
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3. 3
3. 3
3. 3
125
7
127
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3. 3
3. 3
2. 5
125
7
115
Maximum
3.465
3.465
2.625
Units
V
V
V
mA
mA
mA
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
FB_SEL
PLL_BYPASS,
N_SEL0, N_SEL1
FB_SEL
PLL_BYPASS,
N_SEL0, N_SEL1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0. 8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
844246AM
www.icst.com/products/hiperclocks.html
4
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844246
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER W
/I
NTEGRATED
F
ANOUT
B
UFFER
Test Conditions
Minimum
Typical
387
40
1.29
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5% T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
379
40
1.24
50
Maximum
Units
mV
mV
V
mV
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pf parallel resonant crystal.
25
Test Conditions
Minimum
Typical Maximum
33.333
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
844246AM
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5
REV. A SEPTEMBER 29, 2005
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