Changes to Ordering Guide .......................................................... 30
7/04—Revision 0: Initial Version
Rev. F | Page 2 of 28
Data Sheet
SPECIFICATIONS
AD5429/AD5439/AD5449
V
DD
= 2.5 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless
otherwise noted. DC performance is measured with the
OP177,
and ac performance is measured with the
AD8038,
unless otherwise noted.
Table 1.
Parameter
1
STATIC PERFORMANCE
AD5429
Resolution
Relative Accuracy
Differential Nonlinearity
AD5439
Resolution
Relative Accuracy
Differential Nonlinearity
AD5449
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature
Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range
V
REF
A, V
REF
B Input Resistance
V
REF
A-to-V
REF
B Input Resistance
Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output High Voltage, V
OH
Output Low Voltage, V
OL
Input Leakage Current, I
IL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying Bandwidth
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
Digital-to-Analog Glitch Impulse
V
DD
− 1
V
DD
− 0.5
0.4
0.4
1
10
Min
Typ
Max
Unit
Conditions
8
±0.5
±1
10
±0.5
±1
12
±1
−1/+2
±25
±5
±5
±15
±10
11
1.6
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
%
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0x0000, T
A
= 25°C, I
OUT
1
Data = 0x0000, I
OUT
1
9
13
2.5
Input resistance temperature coefficient = −50 ppm/°C
Typical = 25°C, maximum = 125°C
3.5
3.5
1.7
1.7
0.8
0.7
pF
pF
V
V
V
V
V
V
V
V
µA
pF
MHz
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.5 V to 2.7 V
V
DD
= 4.5 V to 5.5 V, I
SOURCE
= 200 µA
V
DD
= 2.5 V to 3.6 V, I
SOURCE
= 200 µA
V
DD
= 4.5 V to 5.5 V, I
SINK
= 200 µA
V
DD
= 2.5 V to 3.6 V, I
SINK
= 200 µA
4
10
V
REF
= ±3.5 V p-p, DAC loaded all 1s
R
LOAD
= 100 Ω, C
LOAD
= 15 pF, V
REF
= 10 V,
DAC latch alternately loaded with 0s and 1s
80
35
30
20
3
120
70
60
40
ns
ns
ns
ns
nV-sec
1 LSB change around major carry, V
REF
= 0 V
Rev. F | Page 3 of 28
AD5429/AD5439/AD5449
Parameter
1
Multiplying Feedthrough Error
Min
Typ
Max
70
48
17
30
5
Unit
dB
dB
pF
pF
nV-sec
nV/√Hz
dB
dB
dB
AD5449,
65k codes, V
REF
= 3.5 V
55
63
65
50
60
62
dB
dB
dB
dB
dB
dB
AD5449,
65k codes, V
REF
= 3.5 V
73
80
87
70
75
80
72
65
2.5
0.5
Power Supply Sensitivity
1
Data Sheet
Conditions
DAC latches loaded with all 0s, V
REF
= ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
V
REF
= 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, V
REF
= 3.5 V
Output Capacitance
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz f
OUT
50 kHz f
OUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
Clock = 25 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
Clock = 25 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
Intermodulation Distortion
f
1
= 40 kHz, f
2
= 50 kHz
f
1
= 40 kHz, f
2
= 50 kHz
POWER REQUIREMENTS
Power Supply Range
I
DD
12
25
3
25
81
61
66
dB
dB
dB
dB
dB
dB
dB
dB
5.5
0.7
10
0.001
V
µA
µA
%/%
AD5449,
65k codes, V
REF
= 3.5 V
Clock = 10 MHz
Clock = 25 MHz
T
A
= 25°C, logic inputs = 0 V or V
DD
T
A
= −40°C to +125°C, logic inputs = 0 V or V
DD
∆V
DD
= ±5%
Guaranteed by design and characterization, not subject to production test.
Rev. F | Page 4 of 28
Data Sheet
TIMING CHARACTERISTICS
AD5429/AD5439/AD5449
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
123
t
13
t
14
Update Rate
1
2
Limit at T
MIN
, T
MAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
12
4.5
2.47
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments
2
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
CLR pulse width
SYNC rising edge to LDAC falling edge
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
Guaranteed by design and characterization, not subject to production test.
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
TIMING DIAGRAMS
t
1
SCLK
t
8
SYNC
t
4
t
2
t
3
t
7
t
6
t
5
SDIN
DB15
DB0
t
9
LDAC
1
t
10
t
11
LDAC
2
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
04464-002
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
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