SN74LVC112ADBRG4 datasheet, PDF

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SN74LVC112ADBRG4: DescriptionFlip Flops Dual Neg Edge Trgerd J K FlipFlop; Categorylogic logic; File Size1MB，25 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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SN74LVC112ADBRG4 Overview

Flip Flops Dual Neg Edge Trgerd J K FlipFlop

SN74LVC112ADBRG4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	SSOP, SSOP16,.3
Contacts	16
Reach Compliance Code	unknown
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	6.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	150000000 Hz
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP16,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	5.9 ns
propagation delay (tpd)	7.1 ns
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	5.3 mm
minfmax	150 MHz

SN74LVC112ADBRG4 Related Products

	SN74LVC112ADBRG4	SN74LVC112ADTG4	SN74LVC112APWG4	SN74LVC112APWTG4	SN74LVC112ADRG4	SN74LVC112ANSRG4	SN74LVC112A
Description	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	Flip Flops Dual Neg Edge Trgerd J K FlipFlop	SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	-
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	-
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-
Parts packaging code	SOIC	SOIC	TSSOP	TSSOP	SOIC	SOIC	-
package instruction	SSOP, SSOP16,.3	SOP, SOP16,.25	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25	SOP, SOP16,.25	SOP, SOP16,.3	-
Contacts	16	16	16	16	16	16	-
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	-
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	-
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	-
JESD-609 code	e4	e4	e4	e4	e4	e4	-
length	6.2 mm	9.9 mm	5 mm	5 mm	9.9 mm	10.2 mm	-
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	-
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	-
Maximum Frequency@Nom-Sup	150000000 Hz	150000000 Hz	150000000 Hz	150000000 Hz	150000000 Hz	150000000 Hz	-
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	-
Humidity sensitivity level	1	1	1	1	1	1	-
Number of digits	2	2	2	2	2	2	-
Number of functions	2	2	2	2	2	2	-
Number of terminals	16	16	16	16	16	16	-
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	SSOP	SOP	TSSOP	TSSOP	SOP	SOP	-
Encapsulate equivalent code	SSOP16,.3	SOP16,.25	TSSOP16,.25	TSSOP16,.25	SOP16,.25	SOP16,.3	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	-
method of packing	TAPE AND REEL	TAPE AND REEL	TUBE	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	-
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	-
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-
Prop。Delay @ Nom-Sup	5.9 ns	5.9 ns	5.9 ns	5.9 ns	5.9 ns	5.9 ns	-
propagation delay (tpd)	7.1 ns	7.1 ns	7.1 ns	7.1 ns	7.1 ns	7.1 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	2 mm	1.75 mm	1.2 mm	1.2 mm	1.75 mm	2 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	1.65 V	-
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	-
surface mount	YES	YES	YES	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	-
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-
Terminal pitch	0.65 mm	1.27 mm	0.65 mm	0.65 mm	1.27 mm	1.27 mm	-
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	-
width	5.3 mm	3.9 mm	4.4 mm	4.4 mm	3.9 mm	5.3 mm	-
minfmax	150 MHz	150 MHz	150 MHz	150 MHz	150 MHz	150 MHz	-

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