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LMUN5215T1

Description
PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-323
CategoryDiscrete semiconductor    The transistor   
File Size129KB,10 Pages
ManufacturerLRC
Websitehttp://www.lrc.cn
Download Datasheet Parametric View All

LMUN5215T1 Overview

PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-323

LMUN5215T1 Parametric

Parameter NameAttribute value
MakerLRC
package instruction,
Reach Compliance Codeunknow
Maximum collector current (IC)0.1 A
Minimum DC current gain (hFE)160
Number of components1
Polarity/channel typeNPN
Maximum power dissipation(Abs)0.31 W
surface mountYES
Transistor component materialsSILICON
LESHAN RADIO COMPANY, LTD.
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network con-
sisting of two resistors; a series base resistor and a base–emitter resistor.
The BRT eliminates these individual components by integrating them into a
single device. The use of a BRT can reduce both system cost and board
space. The device is housed in the SC–70/SOT–323 package which is
designed for low power surface mount applications.
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
The SC–70/SOT–323 package can be soldered using wave or
LMUN5211T1
SERIES
3
1
2
SC-70 / SOT-323
PIN 1
BASE
(INPUT)
R
1
PIN 3
COLLECTOR
(OUTPUT)
R
2
PIN 2
EMITTER
(GROUND)
reflow. The modified gull–winged leads absorb thermal stress
during soldering eliminating the possibility of damage to the die.
• Available in 8 mm embossed tape and reel
Use the Device Number to order the 7 inch/3000 unit reel.
• Pb-Free package is available
MARKINGDIAGRAM
8X
M
DEVICE MARKING INFORMATION
See specific marking information in the device marking table on page 2
of this data sheet.
8x = Specific Device Code
x = (See Marking Table)
M= Date Code
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance –
Junction-to-Ambient
Thermal Resistance –
Junction-to-Lead
Junction and Storage
Temperature Range
1. FR–4 @ Minimum Pad
2. FR–4 @ 1.0 x 1.0 inch Pad
Symbol
P
D
Max
202 (Note 1.)
310 (Note 2.)
1.6 (Note 1.)
2.5 (Note 2.)
618 (Note 1.)
403 (Note 2.)
280 (Note 1.)
332 (Note 2.)
–55 to +150
Unit
mW
mW/°C
°C/W
°C/W
°C
R
θJA
R
θJL
T
J,
T
stg
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