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LMU18: Description16 x 16-bit Parallel Multiplier; File Size147KB，7 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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LMU18 Overview

16 x 16-bit Parallel Multiplier

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LMU18

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

LMU18

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

DESCRIPTION

The

LMU18

is a high-speed, low

power 16-bit parallel multiplier.

The LMU18 is an 84-pin device

which provides simultaneous access

to all outputs.

The LMU18 produces the 32-bit

product of two 16-bit numbers.

Data present at the A inputs, along

with the TCA control bit, is loaded

into the A register on the rising edge

of CLK. B data and the TCB control

bit are similarly loaded. Loading of

the A and B registers is controlled

by the ENA and ENB controls. When

HIGH, these controls prevent appli-

cation of the clock to the respective

specify the operands as two’s com-

plement when HIGH, or unsigned

magnitude when LOW.

RND is loaded on the rising edge of CLK,

providing either ENA or ENB are LOW.

RND, when HIGH, adds ‘1’ to the

most significant bit position of the

least significant half of the product.

Subsequent truncation of the 16 least

significant bits produces a result

correctly rounded to 16-bit precision.

At the output, the Right Shift control (RS)

selects either of two output formats. RS

LOW produces a 31-bit product with a

copy of the sign bit inserted in the MSB

postion of the least significant half. RS

HIGH gives a full 32-bit product. Two

16-bit output registers are provided to

hold the most and least significant

halves of the result (MSP and LSP) as

defined by RS. These registers are loaded

on the rising edge of CLK, subject to the

ENR control. When ENR is HIGH, clock-

ing of the result registers is prevented.

For asynchronous output these registers

may be made transparent by setting the

feed through control (FT) HIGH and

ENR LOW.

The two halves of the product may be

routed to a single 16-bit three-state

output port (MSP) via a multiplexer.

MSPSEL LOW causes the MSP outputs to

be driven by the most significant half of

the result. MSPSEL HIGH routes the

least significant half of the result to the

MSP pins. The MSB of the result is avail-

able in both true and complemented

form to aid implementation of higher

precision multipliers.

FEATURES

35 ns Worst-Case Multiply Time

Low Power CMOS Technology

Full 32-bit Output Port —

No Multiplexing Required

Two’s Complement, Unsigned, or

Mixed Operands

Three-State Outputs

84-pin PLCC, J-Lead

LMU18 B

LOCK

IAGRAM

TCA

CLK

ENA

ENB

15-0

A REGISTER

TCB

15-0

B REGISTER

RND

FORMAT ADJUST

ENR

RESULT

MSPSEL

OEM

31-16

15-0

OEL

Multipliers

08/16/2000–LDS.18-O

LMU18 Related Products

	LMU18	LMU18JC35	LMU18JC45
Description	16 x 16-bit Parallel Multiplier	16 x 16-bit Parallel Multiplier	16 x 16-bit Parallel Multiplier

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