operands in two’s complement format, made in the LMU08 and LMU8U for
proper rounding of the product to
and produces a two’s complement
result. The product is provided in two 8-bit precision. The round input is
loaded at the rising edge of the logical
halves with the sign bit replicated as
the most significant bit of both halves. OR of CLK A and CLK B for the
LMU08. The LMU8U latches RND on
the rising edge of CLK A only. In
either case, a ‘1’ is added in the most
significant position of the lower
A
7-0
B
7-0
product byte when RND is asserted.
8
8
Subsequent truncation of the least
significant product byte results in a
B REGISTER
A REGISTER
correctly rounded 8-bit result.
LMU08 Only
REGISTER
RND
16
8
8
CLK R
RESULT
REGISTER
OEM
8
R
15-8
8
R
7-0
OEL
Multipliers
1
08/16/2000–LDS.08/8U-R
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
F
IGURE
1
A
.
I
NPUT
F
ORMATS
A
IN
LMU08 Fractional Two’s Complement
7 6 5
–2
0
2
–1
2
–2
(Sign)
B
IN
2 1 0
2
–5
2
–6
2
–7
7 6 5
–2
0
2
–1
2
–2
(Sign)
2 1 0
2
–5
2
–6
2
–7
LMU08 Integer Two’s Complement
7 6 5
–2
7
2
6
2
5
(Sign)
2 1 0
2
2
2
1
2
0
7 6 5
–2
7
2
6
2
5
(Sign)
2 1 0
2
2
2
1
2
0
LMU8U Unsigned Fractional
7 6 5
2
–1
2
–2
2
–3
2 1 0
2
–6
2
–7
2
–8
7 6 5
2
–1
2
–2
2
–3
2 1 0
2
–6
2
–7
2
–8
LMU8U Unsigned Integer
7 6 5
2
7
2
6
2
5
2 1 0
2
2
2
1
2
0
7 6 5
2
7
2
6
2
5
2 1 0
2
2
2
1
2
0
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
MSP
LMU08 Fractional Two’s Complement
15 14 13
–2
0
2
–1
2
–2
(Sign)
LSP
10 9 8
2
–5
2
–6
2
–7
7 6 5
–2
0
2
–8
2
–9
(Sign)
2 1 0
2
–12
2
–13
2
–14
LMU08 Integer Two’s Complement
15 14 13
–2
14
2
13
2
12
(Sign)
10 9 8
2
9
2
8
2
7
7 6 5
–2
14
2
6
2
5
(Sign)
2 1 0
2
2
2
1
2
0
LMU8U Unsigned Fractional
15 14 13
2
–1
2
–2
2
–3
10 9 8
2
–6
2
–7
2
–8
7 6 5
2
–9
2
–10
2
–11
2 1 0
2
–14
2
–15
2
–16
LMU8U Unsigned Integer
15 14 13
2
15
2
14
2
13
10 9 8
2
10
2
9
2
8
7 6 5
2
7
2
6
2
5
2 1 0
2
2
2
1
2
0
Multipliers
2
08/16/2000–LDS.08/8U-R
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Typ
Max
Unit
V
0.5
2.0
0.0
V
CC
0.8
±20
±20
8
24
1.0
V
V
V
µA
µA
mA
mA
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
Multipliers
3
08/16/2000–LDS.08/8U-R
432109876543210987654321
432109876543210987654321
432109876543210987654321
432109876543210987654321
*D
ISCONTINUED
S
PEED
G
RADE
Symbol
Symbol
321098765432121 8 5 2 9 6 3 0 7
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
1098765432109876543210987654321
321098765432121098765432109876543210987654321
1
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
32109876543212 09 76 43 10 87 54 21 98 65432
Min
DEVICES INCORPORATED
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
8 x 8-bit Parallel Multiplier
LMU08/8U–
50
35
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
10987654321
210987654321
210987654321
2
Min
21098765432
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
210987654321
0 7
210987654321
210987654321
1
21 98 654321
Min
S
WITCHING
W
AVEFORMS
M
ILITARY
O
PERATING
R
ANGE
(–55°C to +125°C)
Notes 9, 10 (ns)
t
DIS
t
ENA
t
D
t
H
t
S
t
PW
t
MC
t
DIS
t
ENA
t
D
t
H
t
S
t
PW
t
MC
INPUT
CLK R
CLK A
CLK B
OEL
OEM
R
15-0
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
t
S
t
H
t
PW
t
DIS
HIGH IMPEDANCE
t
MC
4
t
PW
14
20
20
25
4
5
70*
90*
t
ENA
Max
Max
22
24
25
70
35
35
35
90
Min
Min
15
20
14
20
2
0
LMU08/8U–
60*
45*
Max
Max
22
22
24
60
20
20
22
50
t
D
Min
Min
15
15
14
10
2
0
Max
Max
20
20
22
35
22
24
22
45
Multipliers
LMU08/8U
Min
08/16/2000–LDS.08/8U-R
10
15
10
0
8
2
20*
25*
Max
Max
15
15
18
20
20
20
20
25
LMU08/8U
DEVICES INCORPORATED
8 x 8-bit Parallel Multiplier
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag-
sources of
I
OH
and
I
OL
respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above
V
CC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
V
CC
+ 0.6 V. The device can withstand installed between
V
CC
and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device
V
CC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and
V
CC
supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and
V
CC
noise to maintain required DUT input
2
F
NCV
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case re-
quirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
V
CC
or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
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