ucts. Accumulation is performed to The ACC and SUB inputs control accu-
27-bit precision with the multiplier prod- mulator operation. ACC HIGH results in
addition of the multiplier product and
uct sign extended as appropriate.
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
A
11-0
B
11-0
HIGH results in subtraction of the accu-
12
12
mulator contents from the multiplier
A REGISTER
B REGISTER
product, with the result stored in the
accumulator register. With ACC LOW
and SUB LOW, no accumulation occurs
and the next product is loaded directly
into the accumulator register. ACC LOW
and SUB HIGH is undefined.
The
LMA1009
and
LMA2009
are high-
speed, low power 12-bit multiplier-accu-
mulators. They are pin-for-pin equiva-
lent to the TRW TDC1009/TMC2009
multiplier-accumulators. The LMA1009
and LMA2009 are functionally identical;
they differ only in packaging. Full ambi-
ent temperature range operation is
achieved by the use of advanced CMOS
technology.
24
R
R + A
R – A
A
27
FEATURES
u
20 ns Multiply-Accumulate Time
u
Low Power CMOS Technology
u
Replaces Fairchild TDC1009/
TMC2009
u
Two’s Complement or Unsigned
Operands
u
Accumulator Performs Preload,
Accumulate, and Subtract
u
Three-State Outputs
u
68-pin PLCC, J-Lead
LMA1009/2009 B
LOCK
D
IAGRAM
CLK A
CLK B
TC
ACC
SUB
REGISTER
RND
OEX
OEM
OEL
PREL
3
OEX
OEM
OEL
PRELOAD
CONTROL
LOGIC
3
LEX
LEM
LEL
PASS R
The LMA1009/2009 output register (ac-
cumulator register) is divided into three
independently controlled sections. The
least significant result (LSR) and most
significant result (MSR) registers are 12
bits in length. The extended result regis-
ter (XTR) is 3 bits long.
Each output register has an independ-
ent output enable control. In addition
to providing control of the three-state
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH, data
can be preloaded via the bidirectional
output pins into the respective output
registers. Data present on the output
pins is latched on the rising edge of
CLK R. The interrelation of PREL and
the enable controls is summarized in
Table 1.
LEX
27
3
LEM
12
LEL
12
CLK R
ACCUMULATOR REGISTER
OEX
3
R
26-24
OEM
12
R
23-12
OEL
12
R
11-0
Multiplier-Accumulators
1
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
F
IGURE
1
A
.
I
NPUT
F
ORMATS
A
IN
B
IN
Fractional Two’s Complement (TC = 1)
11 10 9
–2
0
2
–1
2
–2
(Sign)
T
ABLE
1. P
RELOAD
T
RUTH
T
ABLE
PREL OEX
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
OEM
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OEL
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
XTR
OUT
OUT
OUT
OUT
Z
Z
Z
Z
Z
Z
Z
Z
PREL
PREL
MSR LSR
OUT OUT
OUT
Z
Z
Z
OUT
Z
2 1 0
2
–9
2
–10
2
–11
11 10 9
–2
0
2
–1
2
–2
(Sign)
2 1 0
2
–9
2
–10
2
–11
OUT OUT
OUT
Z
Z
Z
Z
PREL
Z
OUT
Z
Z
PREL
Z
Integer Two’s Complement (TC = 1)
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
Unsigned Fractional (TC = 0)
11 10 9
2
–1
2
–2
2
–3
2 1 0
2
–10
2
–11
2
–12
11 10 9
2
–1
2
–2
2
–3
2 1 0
2
–10
2
–11
2
–12
PREL PREL
Z
Z
Z
PREL
Z
PREL PREL
PREL PREL PREL
Unsigned Integer (TC = 0)
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
PREL = Preload data to appropriate register
OUT = Register available on output pins
Z
= High impedance state
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
XTR
MSR
Fractional Two’s Complement
26 25 24
–2
4
2
3
2
2
(Sign)
LSR
23 22 21
2
1
2
0
2
–1
14 13 12
2
–8
2
–9
2
–10
11 10 9
2
–11
2
–12
2
–13
2 1 0
2
–20
2
–21
2
–22
Integer Two’s Complement
26 25 24
–2
26
2
25
2
24
(Sign)
23 22 21
2
23
2
22
2
21
14 13 12
2
14
2
13
2
12
Unsigned Fractional
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
26 25 24
2
2
2
1
2
0
23 22 21
2
–1
2
–2
2
–3
14 13 12
2
–10
2
–11
2
–12
Unsigned Integer
11 10 9
2
–13
2
–14
2
–15
2 1 0
2
–22
2
–23
2
–24
26 25 24
2
26
2
25
2
24
23 22 21
2
23
2
22
2
21
14 13 12
2
14
2
13
2
12
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
Multiplier-Accumulators
2
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Typ
Max
Unit
V
0.5
2.0
0.0
V
CC
0.8
±20
±20
12
25
1.0
V
V
V
µA
µA
mA
mA
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
Multiplier-Accumulators
3
03/29/2000–LDS.10/2009-L
432109876543210987654321
432109876543210987654321
432109876543210987654321
*D
ISCONTINUED
S
PEED
G
RADE
Symbol
Symbol
*includes OEX, OEM, OEL
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321
Min
20
20
20
2
2
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
32109876543210987654321
2 9 6 3 0 7
1
32109876543210987654321
32109876543210987654321
3 10 87 54 21 98 65432
Min
15
15
15
2
2
DEVICES INCORPORATED
S
WITCHING
W
AVEFORMS
M
ILITARY
O
PERATING
R
ANGE
(–55°C to +125°C)
Notes 9, 10 (ns)
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
t
DIS
t
ENA
t
D
t
HP
t
SP
t
H
t
S
t
PW
t
MC
t
DIS
t
ENA
t
D
t
HP
t
SP
t
H
t
S
t
PW
t
MC
CLK R
CLK A
CLK B
PREL
R
26-0
A
11-0
B
11-0
OE*
Parameter
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Preload Hold Time
Preload Setup Time
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Delay
Preload Hold Time
Preload Setup Time
Input Register Hold Time
Input Register Setup Time
Clock Pulse Width
Clocked Multiply Time
t
SP
PRELOAD
t
HP
t
PW
t
S
t
DIS
4
t
H
t
PW
HIGH IMPEDANCE
t
PW
12 x 12-bit Multiplier-Accumulator
95*
75*
t
MC
Max
Max
30
35
25
30
35
30
95
75
t
ENA
Min
Min
15
15
20
20
15
20
2
2
2
2
Multiplier-Accumulators
LMA1009/2009–
65*
55*
LMA1009/2009–
55*
45
Max
Max
25
30
25
55
30
35
30
65
Min
Min
t
D
12
15
12
15
15
15
2
2
2
2
LMA 1009/2009
Max
Max
03/29/2000–LDS.10/2009-L
25
25
25
45
30
30
25
55
OUTPUT
Min
Min
12
10
12
10
10
2
2
2
8
2
25*
20
Max
Max
20
20
20
25
18
18
18
20
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag-
sources of
I
OH
and
I
OL
respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above
V
CC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
V
CC
+ 0.6 V. The device can withstand installed between
V
CC
and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device
V
CC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and
V
CC
supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and
V
CC
noise to maintain required DUT input
2
F
NCV
levels relative to the DUT ground pin.
where
4
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case re-
quirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
V
CC
or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
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