A500K050-BGG272 datasheet, PDF

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A500K050-BGG272: DescriptionField Programmable Gate Array, 5376-Cell, CMOS, PBGA272; CategoryProgrammable logic devices Programmable logic; File Size2MB，72 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A500K050-BGG272 Overview

Field Programmable Gate Array, 5376-Cell, CMOS, PBGA272

A500K050-BGG272 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	BGA, BGA272,20X20,50
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B272
Number of entries	210
Number of logical units	5376
Output times	206
Number of terminals	272
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA272,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	2.5,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Base Number Matches	1

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v3.0

ProASIC

™

500K Family

Fe a t ur es an d B e ne f i ts

High C apaci t y

I/O

• 100,000 to 475,000 System Gates

• 14k to 63k Bits of Two-Port SRAM

• 106 to 440 User I/Os

P erf orm a nce

• Mixed 2.5V/3.3V Support with Individually-Selectable

Voltage and Slew Rate

• 3.3V, PCI Compliance (PCI Revision 2.2)

S ecur e Pr og ram m i ng

The Industry’s Most Effective Security Key Prevents Read

Back of Programming Bit Stream

S ta ndar d FP GA and AS IC De si gn F low

• 33 MHz PCI 32-bit PCI

• Internal System Performance up to 250 MHz

• External System Performance up to 100 MHz

Low P ower

• Low Impedance Flash Switches

• Segmented Hierarchical Routing Structure

• Small, Efficient Logic Cells

H ig h P er f o r m ance R ou t ing H i e ra rc hy

• Flexibility with Choice of Industry-Standard Front-End

Tools

• Efficient Design Through Front-End Timing and Gate

Optimization

IS P S uppo rt

• In-System Programming (ISP) with Silicon Sculptor and

Flash Pro

S RA Ms and FIFO s

•

Ultra Fast Local Network

Efficient Long Line Network

High Speed Very Long Line Network

High Performance Global Network

• Up to 150 MHz Synchronous and Asynchronous Operation

• Netlist Generator Ensures Optimal Usage of Embedded

Memory Blocks

Bo undar y S can T es t

Nonv ola ti le and R epr ogr am m abl e F las h

T echno log y

IEEE Std. 1149.1 (JTAG) Compliant

• Live at Power Up

• No Configuration Device Required

• Retains Programmed Design During Power-Down/

Power-Up Cycles

Pr oA S I C Pr o d uc t P r of i l e

Device

Maximum System Gates

Typical Gates

Maximum Flip-Flops

Embedded RAM Bits

Embedded RAM Blocks (256 X 9)

Logic Tiles

Global Routing Resources

Maximum User I/Os

JTAG

PCI

Package

(by Pin Count)

PQFP

PBGA

FBGA

A500K050

100,000

43,000

5,376

14k

5,376

204

Yes

208

272

144

A500K130

290,000

105,000

12,800

45k

12,800

306

Yes

208

272, 456

144, 256

A500K180

370,000

150,000

18,432

54k

18,432

362

Yes

208

456

256

A500K270

475,000

215,000

26,880

63k

26,880

440

Yes

208

456

256, 676

F eb r u a r y 2 0 0 2

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