Burr Brown Products
from Texas Instruments
ADS8406
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER
SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Pseudo-Bipolar, Fully Differential Input, -V
REF
to V
REF
16-Bit NMC at 1.25 MSPS
±2
LSB INL Max, -1/+1.25 LSB DNL
90 dB SNR, -95 dB THD at 100 kHz Input
Zero Latency
Internal 4.096 V Reference
High-Speed Parallel Interface
Single 5 V Analog Supply
Wide I/O Supply: 2.7 V to 5.25 V
Low Power: 155 mW at 1.25 MHz Typ
Pin Compatible With ADS8412/8402
48-Pin TQFP Package
APPLICATIONS
•
•
•
•
•
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DWDM
Instrumentation
High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
Transducer Interface
Medical Instruments
Communications
DESCRIPTION
The ADS8406 is a 16-bit, 1.25 MHz A/D converter
with an internal 4.096-V reference. The device in-
cludes a 16-bit capacitor-based SAR A/D converter
with inherent sample and hold. The ADS8406 offers a
full 16-bit interface and an 8-bit option where data is
read using two 8-bit read cycles.
The ADS8406 has a pseudo-bipolar, fully differential
input. It is available in a 48-lead TQFP package and
is characterized over the industrial -40°C to 85°C
temperature range.
High Speed SAR Converter Family
Type/Speed
18 Bit Pseudo-Diff
16 Bit Pseudo-Diff
16 Bit Pseudo Bipolar,
Fully Differential
14 Bit Pseudo-Diff
12 Bit Pseudo-Diff
500 kHz
ADS8383
580 kHz
ADS8381
ADS8371
ADS8401
ADS8405
ADS8402
ADS8406
ADS7890 (S)
ADS7891
ADS7881
ADS8412
ADS8411
750 MHZ
1.25 MHz
2 MHz
3 MHz
4 MHz
SAR
+IN
−IN
REFIN
4.096-V
Internal
Reference
+
_
CDAC
Comparator
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
Parallel DATA
Output Bus
REFOUT
Clock
Conversion
and
Control Logic
RESET
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
ADS8406
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
www.ti.com
ORDERING INFORMATION
(1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIG-
NATOR
TEMPERA-
TURE
RANGE
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
Tape and reel
250
Tape and reel
1000
Tape and reel
250
Tape and reel
1000
ADS8406I
–4 to +4
–2 to +2
15
48 Pin
TQFP
ADS8406IPFBT
PFB
–40°C to 85°C
ADS8406IPFBR
ADS8406IBPFBT
PFB
–40°C to 85°C
ADS8406IBPFBR
ADS8406IB
–2 to +2
–1 to +1.25
16
48 Pin
TQFP
(1)
For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Voltage
+IN to AGND
–IN to AGND
+VA to AGND
Voltage range
+VBD to BDGND
+VA to +VBD
Digital input voltage to BDGND
Digital output voltage to BDGND
T
A
T
stg
Operating free-air temperature range
Storage temperature range
Junction temperature (T
J
max)
TQFP package
Power dissipation
θ
JA
thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
–0.4 V to +VA + 0.1 V
–0.4 V to +VA + 0.1 V
–0.3 V to 7 V
–0.3 V to 7 V
–0.3 V to 2.55 V
–0.3 V to +VBD + 0.3 V
–0.3 V to +VBD + 0.3 V
–40°C to 85°C
–65°C to 150°C
150°C
(T
J
Max - T
A
)/θ
JA
86°C/W
215°C
220°C
Lead temperature, soldering
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8406
www.ti.com
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
SPECIFICATIONS
T
A
= –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 1.25 MHz (unless otherwise noted)
PARAMETER
ANALOG INPUT
Full-scale input voltage
Absolute input voltage
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
DNL
E
O
E
G
CMRR
Integral linearity
(2) (3)
(1)
TEST CONDITIONS
+IN – (–IN)
+IN
–IN
MIN
–V
ref
–0.2
–0.2
TYP
MAX
V
ref
V
ref
+ 0.2
V
ref
+ 0.2
UNIT
V
V
pF
nA
Bits
Bits
25
0.5
16
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
At dc (0.2 V around V
ref
/2)
+IN – (–IN) = 1 V
pp
at 1 MHz
At 7FFFh output code, +VA
= 4.75 V to 5.25 V, V
ref
=
4.096 V
(4)
500
150
1.25
2
25
100
100
V
IN
= 8 V
pp
at 100 kHz
V
IN
= 8 V
pp
at 500 kHz
V
IN
= 8 V
pp
at 100 kHz
V
IN
= 8 V
pp
at 100 kHz
V
IN
= 8 V
pp
at 100 kHz
V
IN
= 8 V
pp
at 500 kHz
–95
–90
90
88
95
93
5
2.5
4.096
500
4.2
15
16
–4
–2
–2
–1
–2.5
–1.5
–0.12
–0.098
80
80
2
±2
±1
±1
±0.5
±1
±0.5
4
2
2
1.25
2.5
1.5
0.12
0.098
LSB
LSB
mV
mV
%FS
dB
Differential linearity
Offset error
(4)
Gain error
(4) (5)
Common mode rejection ratio
PSRR
DC Power supply rejection ratio
LSB
SAMPLING DYNAMICS
Conversion time
Acquisition time
Throughput rate
Aperture delay
Aperture jitter
Step response
Overvoltage recovery
DYNAMIC CHARACTERISTICS
THD
SNR
SINAD
SFDR
Total harmonic distortion
Signal-to-noise ratio
Signal-to-noise + distortion
Spurious free dynamic range
-3dB Small signal bandwidth
EXTERNAL VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, V
ref
Reference resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(7)
(6)
650
ns
ns
MHz
ns
ps
ns
ns
dB
dB
dB
dB
MHz
V
kΩ
Ideal input span, does not include gain or offset error.
LSB means least significant bit
This is endpoint INL, not best fit.
Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V
This specification does not include the internal reference voltage error and drift.
Calculated on the first nine harmonics of the input frequency
Can vary
±20%
3
ADS8406
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
www.ti.com
SPECIFICATIONS (continued)
T
A
= –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 1.25 MHz (unless otherwise noted)
PARAMETER
INTERNAL REFERENCE OUTPUT
Internal reference start-up time
V
ref
Reference voltage
Source current
Line regulation
Drift
DIGITAL INPUT/OUTPUT
Logic family — CMOS
V
IH
V
IL
V
OH
V
OL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Data format — 2's complement
POWER SUPPLY REQUIREMENTS
Power supply voltage
Supply current,
P
D
T
A
(8)
+VA
(8)
+VBD
+VA
f
s
= 1.25 MHz
f
s
= 1.25 MHz
–40
2.7
4.75
3
5
31
155
5.25
5.25
34
170
85
V
V
mA
mW
°C
I
IH
= 5 µA
I
IL
= 5 µA
I
OH
= 2 TTL loads
I
OL
= 2 TTL loads
+VBD – 1
–0.3
+VBD – 0.6
0
+VBD + 0.3
0.8
+VBD
0.4
V
From 95% (+VA) with 1-µF
storage capacitor
IOUT = 0
Static load
+VA = 4.75 to 5.25 V
IOUT = 0
0.6
36
4.065
4.096
120
4.13
10
ms
V
µA
mV
PPM/°C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power dissipation
(8)
Operating free-air temperature
TEMPERATURE RANGE
This includes only +VA current. +VBD current is typically 1 mA with 5-pF load capacitance on output pins.
4
ADS8406
www.ti.com
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V
PARAMETER
t
CONV
t
ACQ
t
pd1
t
pd2
t
w1
t
su1
t
w2
t
w3
t
w4
t
h1
t
d1
t
su2
t
w5
t
en
t
d2
t
d3
t
w6
t
w7
t
h2
t
su3
t
h3
t
dis
t
d5
t
su4
t
d6
t
d7
t
su(AB)
Conversion time
Acquisition time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, First data bus data transition (RD low, or CS low for
read cycle, or BYTE input changes) after CONVST low
Delay time, CS low to RD low (or BUSY low to RD low when CS =
0)
Setup time, RD high to CS high
Pulse duration, RD low time
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
Pulse duration, CS high time
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data
bus
Delay time, end of conversion to MSB data valid
Byte transition setup time, from BYTE transition to next BYTE
transition
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS =
0 and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
50
50
50
60
500
0
2
20
20
50
0
0
20
10
20
40
0
0
50
20
Min(t
ACQ
)
610
20
0
20
10
(1) (2) (3)
MIN
500
150
TYP
MAX
650
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
5
t
su5
t
h4
(1)
(2)
(3)
MAX(t
CONV
) + MAX(t
d5
)
MIN(t
CONV
)
ns
ns
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See timing diagrams.
All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5
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