5962-8515401CA datasheet, PDF - EEWORLD Datasheet

5962-8515401CA: DescriptionHigh Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125; Categorylogic logic; File Size972KB，18 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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5962-8515401CA Overview

High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125

Parameter Name	Attribute value
Brand Name	Texas Instruments
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP-14
Contacts	14
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	1 week
Is Samacsys	N
series	HC/UH
JESD-30 code	R-GDIP-T14
length	19.56 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	20000000 Hz
MaximumI(ol)	-0.006 A
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/6 V
Maximum supply current (ICC)	0.04 mA
Prop。Delay @ Nom-Sup	51 ns
propagation delay (tpd)	255 ns
Certification status	Qualified
Schmitt trigger	No
Filter level	MIL-PRF-38535
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	6.67 mm
minfmax	23 MHz
Base Number Matches	1

	5962-8515401CA	CD54HC107F3A	CD54HC107	CD74HC107	CD74HCT107
Description	High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125	CD54HC107 High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset	CD74HC107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset	CD74HCT107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Schmitt trigger	No	No	No	No	No
Voltage(Nom)(V)	-	-	3.3,5	3.3,5	5
F @ nom voltage(Max)(Mhz)	-	-	70	70	25
Technology Family	-	-	HC	HC	HCT
Rating	-	-	Military	Catalog	Catalog
IOL(Max)(mA)	-	-	-6	6	6
IOH(Max)(mA)	-	-	6	-6	-6
VCC(Max)(V)	-	-	6	6	5.5
ICC @ nom voltage(Max)(mA)	-	-	0.04	0.04	0.04
tpd @ nom Voltage(Max)(ns)	-	-	51	51	43
VCC(Min)(V)	-	-	2	2	4.5
Package Group	-	-	CDIP\|14	PDIP\|14,SOIC\|14	PDIP\|14
Bits(#)	-	-	2	2	2

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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