CD54HCT74F3A datasheet, PDF - EEWORLD Datasheet

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CD54HCT74F3A: DescriptionHigh Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125; Categorylogic logic; File Size976KB，19 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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CD54HCT74F3A Overview

High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125

CD54HCT74F3A Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	6 weeks
series	HCT
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.56 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	16000000 Hz
MaximumI(ol)	0.004 A
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	0.16 mA
propagation delay (tpd)	53 ns
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	16 MHz

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Description	High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset 14-CDIP -55 to 125	CD54HC74 High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset	CD54HCT74 High Speed CMOS Logic Dual Positive-Edge Trigger D Flip-Flops with Set and Reset	CD74HC74 High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset	CD74HCT74 High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-	-	-	-
Parts packaging code	DIP	DIP	DIP	DIP	DIP	-	-	-	-
package instruction	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	-	-	-	-
Contacts	14	14	14	14	14	-	-	-	-
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	-	-	-	-
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	-	-	-	-
Factory Lead Time	6 weeks	6 weeks	6 weeks	1 week	6 weeks	-	-	-	-
series	HCT	HCT	HC/UH	HC	HCT	-	-	-	-
JESD-30 code	R-GDIP-T14	R-GDIP-T14	R-GDIP-T14	R-GDIP-T14	R-GDIP-T14	-	-	-	-
length	19.56 mm	19.56 mm	19.56 mm	19.56 mm	19.56 mm	-	-	-	-
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	-	-	-	-
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	-	-	-	-
Maximum Frequency@Nom-Sup	16000000 Hz	16000000 Hz	20000000 Hz	20000000 Hz	16000000 Hz	-	-	-	-
MaximumI(ol)	0.004 A	0.004 A	0.0052 A	0.0052 A	0.004 A	-	-	-	-
Number of digits	1	1	1	1	1	-	-	-	-
Number of functions	2	2	2	2	2	-	-	-	-
Number of terminals	14	14	14	14	14	-	-	-	-
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	-	-	-	-
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-	-	-	-
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-	-	-	-
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	-	-	-	-
encapsulated code	DIP	DIP	DIP	DIP	DIP	-	-	-	-
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	-	-	-	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	-	-
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	-	-	-	-
method of packing	TUBE	TUBE	TUBE	TUBE	TUBE	-	-	-	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	-
power supply	5 V	5 V	2/6 V	2/6 V	5 V	-	-	-	-
Maximum supply current (ICC)	0.16 mA	0.04 mA	0.04 mA	0.04 mA	0.16 mA	-	-	-	-
propagation delay (tpd)	53 ns	53 ns	265 ns	265 ns	53 ns	-	-	-	-
Certification status	Not Qualified	Qualified	Not Qualified	Not Qualified	Not Qualified	-	-	-	-
Maximum seat height	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	-	-	-	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	6 V	6 V	5.5 V	-	-	-	-
Minimum supply voltage (Vsup)	4.5 V	4.5 V	2 V	2 V	4.5 V	-	-	-	-
Nominal supply voltage (Vsup)	5 V	5 V	4.5 V	4.5 V	5 V	-	-	-	-
surface mount	NO	NO	NO	NO	NO	-	-	-	-
technology	CMOS	CMOS	CMOS	CMOS	CMOS	-	-	-	-
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	-	-	-	-
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	-	-	-	-
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	-	-	-	-
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	-	-	-	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	-
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-	-	-	-
width	7.62 mm	6.67 mm	7.62 mm	7.62 mm	7.62 mm	-	-	-	-
minfmax	16 MHz	16 MHz	23 MHz	23 MHz	16 MHz	-	-	-	-

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