Product Specification
PE42452
Product Description
The PE42452 is a HaRP™ technology-enhanced
absorptive SP5T RF switch designed for use in 3G/4G
wireless infrastructure and other high performance RF
applications.
This switch is a pin-compatible upgraded version of the
PE42451 with 1.8V control logic. It is comprised of five
symmetric RF ports and has very high isolation. An
integrated CMOS decoder facilitates a three-pin low
voltage CMOS control interface and an external negative
supply option. In addition, no external blocking
capacitors are required if 0V DC is present on the RF
ports.
The PE42452 is manufactured on Peregrine’s
UltraCMOS
®
process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS
®
process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
ESD
UltraCMOS
®
SP5T RF Switch
450–4000 MHz
Features
Five symmetric, absorptive RF ports
High isolation
61 dB @ 900 MHz
55 dB @ 2100 MHz
52 dB @ 2700 MHz
44 dB @ 4000 MHz
High linearity
IIP2 of 96 dBm
IIP3 of 57 dBm
1.8V control logic compatible
105°C operating temperature
Fast switching time of 265 ns
Three pin CMOS logic control
External negative supply option
ESD performance
4kV HBM on RF pins to GND
1.5kV HBM on all pins
Figure 2. Package Type
24-lead 4x4 mm QFN
RF1
RF5
ESD
ESD
50
50
RF4
ESD
ESD
RF2
50
50
RF3
ESD
CMOS Control/
Driver and ESD
50
V1 V2 V3 V
DD
Vss
EXT
(optional)
Document No. DOC-14014-3
│
www.psemi.com
DOC-02114
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE42452
Product Specification
Table 1. Electrical Specifications @ 25°C (Z
S
= Z
L
= 50Ω )
unless otherwise noted
Normal mode
1
: V
DD
= 3.3V, Vss
EXT
= 0V or Bypass mode
2
: V
DD
= 3.3V, Vss
EXT
= -3.3V
Parameter
Operating frequency
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
450 MHz–900 MHz
900 MHz–2100 MHz
2100 MHz–2700 MHz
2700 MHz–4000 MHz
450–4000 MHz
450–4000 MHz
1950 MHz
1950 MHz
1950 MHz
50% control to 10% or 90% RF
56
52
49
41
56
51
49
41
Path
Condition
Min
450
0.95
1.15
1.30
1.60
61
55
52
44
60
53
52
42
16
23
35
96
57
265
345
Typ
Max
4000
1.15
1.35
1.55
1.90
Unit
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
ns
Insertion loss
RFC–RFX
Isolation
RFC–RFX
Isolation
RFX–RFX
Return loss (active port)
Return loss (terminated port)
Input 0.1 dB compression point
3
Input IP2
Input IP3
Switching time
RFX
RFX
RFC–RFX
RFC–RFX
RFC–RFX
Notes: 1. Normal mode: single external positive supply used
2. Bypass mode: both external positive supply and external negative supply used
3. The input 0.1 dB compression point is a linearity figure of merit. Refer to
Table 3
for the operating RF input power (50Ω)
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. DOC-14014-3
│
UltraCMOS
®
RFIC Solutions
PE42452
Product Specification
Figure 3. Pin Configuration (Top View)
Vss
EXT
Table 3. Operating Ranges
Parameter
Symbol
Min
Typ
Max
Unit
Normal mode
1
Supply voltage
Supply current
Bypass mode
2
Supply voltage
Supply current
Negative supply
voltage
Normal or Bypass mode
V
DD
I
DD
Vss
EXT
-3.6
2.7
50
-3.2
5.5
V
µA
V
V
DD
I
DD
2.3
110
5.5
V
µA
GND
GND
GND
RFC
24
23
22
21
20
11
10
12
7
8
9
19
V3
GND
GND
GND
GND
RF3
RF2
Digital input high
(V1, V2, V3)
Digital input low
(V1, V2, V3)
Digital input current
3
V
IH
V
IL
I
CTRL
P
MAX,CW
P
MAX,TERM
T
OP
1.17
-0.3
3.6
0.6
1
33
24
V
V
µA
dBm
dBm
°C
Table 2. Pin Descriptions
Pin #
1, 3, 4, 6, 7,
9, 10, 12, 13,
15, 21, 23, 24
2
5
8
11
14
16
17
18
19
20
22
Pad
Name
GND
RF5
1
RF4
1
RF3
1
RF2
1
RF1
1
V
DD
V1
V2
V3
Vss
EXT2
RFC
1
GND
Ground
RF port 5
RF port 4
RF port 3
RF port 2
RF port 1
Supply voltage
Digital control logic input 1
Digital control logic input 2
Digital control logic input 3
External Vss negative voltage control/
ground
RF common
Exposed pad: Ground for proper operation
Description
RF input power, CW
RF input power into
terminated ports, CW
Operating
temperature range
Notes:
-40
+105
1. Normal mode: connect pin 20 to GND to enable internal negative
voltage generator
2. Bypass mode: apply a negative voltage to Vss
EXT
(pin 20) to
bypass and disable internal negative voltage generator
3. The pull-down resistor in the EVK schematic may increase control
current
Table 4. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Voltage on any DC input
Maximum input power
Storage temperature range
ESD voltage HBM
1
All pins
RF pins to ground
ESD voltage MM
2
, all pins
ESD voltage CDM
3
, all pins
Symbol
V
DD
V
I
P
MAX,ABS
T
ST
V
ESD,HBM
V
ESD,MM
V
ESD,CDM
-60
Min
-0.3
-0.3
Max
5.5
3.6
34
+150
1500
4000
100
500
Unit
V
V
dBm
°C
V
V
V
V
Notes: 1. RF pins 2, 5, 8, 11, 14, and 22 must be at 0V DC. The RF pins do
not require DC blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use Vss
EXT
(pin 20, refer to
Table 3)
to bypass and disable internal
negative voltage generator. Connect Vss
EXT
(pin 20, Vss
EXT
= GND) to
enable internal negative voltage generator
Notes: 1. Human Body Model (MIL_STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model ( JEDEC JESD22-C101D)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Document No. DOC-14014-3
│
www.psemi.com
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE42452
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Switching Frequency
The PE42452 has a maximum 25 kHz switching
rate in normal mode (pin 20 = GND). A faster
switching rate is available in bypass mode (pin 20
= Vss
EXT
). The rate at which the PE42452 can be
switched is then limited to the switching time as
specified in
Table 1.
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42452 in the 24-lead 4x4 QFN package is
MSL1.
Table 5. Truth Table
Mode
All off
RF1 on
RF2 on
RF3 on
RF4 on
RF5 on
All off
Unsupported
V3
0
0
0
0
1
1
1
1
V2
0
0
1
1
0
0
1
1
V1
0
1
0
1
0
1
0
1
Note: Logic State 111 is unsupported and should not be used under any
operating conditions
Optional External Vss Control (VssEXT)
For applications the require a faster switching rate
or spur-free performance, this part can be
operated in bypass mode. Bypass mode requires
an external negative voltage in addition to an
external V
DD
supply voltage.
As specified in
Table 3,
the external negative
voltage (Vss
EXT
) when applied to pin 20 will
disable and bypass the internal negative voltage
generator.
Spurious Performance
The typical low-frequency spurious performance
of the PE42452 in normal mode is –120 dBm
(pin 20 = GND). If spur-free performance is
desired, the internal negative voltage generator
can be disabled by applying a negative voltage to
Vss
EXT
(pin 20).
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. DOC-14014-3
│
UltraCMOS
®
RFIC Solutions
PE42452
Product Specification
Typical Performance Data @ 25°C and V
DD
= 3.3V
unless otherwise noted
Figure 4. Insertion Loss (All Paths)
Figure 5. Insertion Loss vs Temp (RFC–RFX)
Figure 6. Insertion Loss vs V
DD
(RFC–RFX)
Document No. DOC-14014-3
│
www.psemi.com
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
京公网安备 11010802033920号
EEWORLD
