LH5P832
FEATURES
•
32,768
×
8 bit organization
•
Access time: 100/120 ns (MAX.)
•
Cycle time: 160/190 ns (MIN.)
•
Power consumption:
Operating: 357.5/303 mW
Standby: 16.5 mW
•
TTL compatible I/O
•
256 refresh cycle/4 ms
•
Auto refresh is executed by internal
counter (controlled by OE/RFSH pin)
•
Self refresh is executed by internal timer
•
Single +5 V power supply
•
Packages:
28-pin, 600-mil DIP
28-pin, 300-mil SK-DIP
28-pin, 450-mil SOP
DESCRIPTION
The LH5P832 is a 256K bit Pseudo-Static RAM or-
ganized as 32,768
×
8 bits. It is fabricated using sili-
con-gate CMOS process technology.
The LH5P832 uses convenient on-chip refresh cir-
cuitry with a DRAM memory cell for pseudo static
operation. This simplifies external clock inputs, while
providing the same simple, non-multiplexed pinout as
industry standard SRAMs. Moreover, due to the func-
tional similarities between PSRAMs and SRAMs, many
32K
×
8 SRAM sockets can be filled with the LH5P832
with little or no changes. The advantage is the cost
savings realized with the lower cost PSRAM.
CMOS 256K (32K
×
8) Pseudo-Static RAM
The LH5P832 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
standby power, and a simple interface.
Three methods of refresh control are provided for
maximum versatility. A ‘CE-Only’ refresh cycle re-
freshes the addressed row of memory cells transpar-
ently. All 256 rows must be refreshed or accessed every
four milliseconds. ‘Auto Refresh’ automatically cycles
through a different row on every OE/RFSH clock pulse,
accomplishing the row refreshes without the need to
supply row addresses externally. ‘Self Refresh’ further
simplifies the refresh requirements by eliminating the
need for address inputs and clock pulses entirely. An
automatic timer senses time periods when memory
accesses have ceased, and provides full refresh of all
rows of memory without any external assistance.
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
R/W
A
13
A
8
A
9
A
11
OE/RFSH
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5P832-1
TOP VIEW
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1
CMOS 256K (32K
×
8) Pseudo-Static RAM
LH5P832
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on any pin
Output short circuit current
Power dissipation
Operating temperature
Storage temperature
NOTE:
1. Referenced to GND
V
T
I
O
P
D
Topr
Tstg
-1.0 to +7.0
50
600
0 to +70
-55 to +150
V
mA
mW
°C
°C
1
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
V
CC
V
IH
V
IL
4.5
2.4
-1.0
5.0
5.5
V
CC
+ 0.3
+0.8
V
V
V
CAPACITANCE (V
CC
= 5.0 V
±10%,
T
A
= 0 to +70°C, f = 1 MHz)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
Input capacitance
Input/output capacitance
A
0
- A
14
, R/W
CE, OE/RFSH
I/O
1
- I/O
8
C
IN1
C
IN2
C
OUT1
8
5
12
pF
pF
pF
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Operating current
Operating current
Standby current
Self refresh average current
CPU internal cycle
average current
CPU internal cycle
average current
Input leakage current
Output leakage current
Output High voltage
Output Low voltage
I
CC1
I
CC1
I
CC2
I
CC3
I
CC4
I
CC4
I
LI
I
LO
V
OH
V
OL
tRC = 160 ns
tRC = 190 ns
CE = V
IH
, OE/RFSH = V
IH
CE = V
IH
, OE/RFSH = V
IL
tRC = 160 ns
tRC = 190 ns
0 V
≤
V
IN
≤
6.5 V
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V
I
OUT
= -1 mA
I
OUT
= 4 mA
-10
-10
2.4
65
55
3
3
65
55
10
10
0.4
mA
mA
mA
mA
mA
mA
µA
µA
V
V
1, 2
1, 2
1
1
1, 2
1, 2
3
NOTES:
1. Specified values are with outputs open.
2. I
CC1
and I
CC4
depend on the cycle time.
3. The output pins are in high-impedance state.
AC TEST CONDITIONS
PARAMETER
MODE
NOTE
Input voltage amplitude
Input rise/fall time
Timing reference level
Output load conditions
NOTE:
1. Includes scope and jig capacitance.
0.6 to 2.4 V
5 ns
1.5 V
1TTL gate, C
L
= 100 pF
1
3
LH5P832
CMOS 256K (32K
×
8) Pseudo-Static RAM
AC CHARACTERISTICS
READ AND WRITE CYCLES
1,2
(V
CC
= 5.0 V
±10%,
T
A
= 0 to 70°C)
PARAMETER
SYMBOL
MIN.
160 ns
MAX.
MIN.
190 ns
MAX.
UNIT
NOTE
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command hold time
Read command setup time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Output enable from end of write
Chip disable to output in High-Z
Output disable to output in High-Z
Write enable to output in High-Z
OE setup time
OE hold time
OE lead time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write
Data setup time from CE
Data hold time from write
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
t
RC
t
RMW
t
CE
t
P
t
AS
t
AH
t
RCH
t
RCS
t
CEA
t
OEA
t
CLZ
t
OLZ
t
WLZ
t
CHZ
t
OHZ
t
WHZ
t
OES
t
OEH
t
OEL
t
WCP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
T
t
REF
160
225
100
50
0
20
0
0
100
40
10
0
0
0
0
0
10
0
10
60
60
60
40
40
0
0
3
35
4
30
30
30
10,000
190
280
120
60
0
30
0
0
120
50
10
0
0
0
0
0
10
0
10
85
85
85
50
50
0
0
3
35
4
35
35
35
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
2
2
2
3
3
REFRESH CYCLE
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time
(Auto refresh)
CE delay time from refresh active
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh
precharge (Self refresh)
t
FC
t
RFD
t
FAP
t
FP
t
FCE
t
FAS
t
FRS
160
50
60
30
190
8,000
190
8,000
190
60
80
30
225
8,000
225
8,000
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. At least 200
µs
of pause time after power on should be given for
proper device operation.
CE and OE/RFSH must be fixed at V
IH
for 200
µs
from the V
DD
reached to the specified voltage level
and followed by at least 8 dummy cycles.
2. AC characteristics are measured at t
T
= 5 ns.
3. Measured with a load circuit equivalent to 1TTL loads and
100 pF.
4
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