LH52D1000
FEATURES
•
Access time: 85 ns (MAX.),
100 ns (MAX.)
•
Current consumption:
Operating: 40 mA (MAX.)
6 mA (MAX.) (t
RC
, t
WC
= 1
µs)
Standby: 45
µA
(MAX.)
•
Data Retention:
1.0
µA
(MAX. V
CCDR
= 3 V, t
A
= 25°C)
•
Single power supply: 2.7 V to 3.6 V
•
Operating temperature: -40°C to +85°C
•
Fully-static operation
•
Three-state output
•
Not designed or rated as radiation
hardened
•
Packages:
32-pin 8
×
20 mm
2
TSOP
32-pin 8
×
13.4 mm
2
STSOP
•
N-type bulk silicon
DESCRIPTION
The LH52D1000 is a static RAM organized as
131,072
×
8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
CMOS 1M (128K
×
8) Static Ram
PIN CONNECTIONS
32-PIN TSOP
32-PIN STSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
52D1000S-1
Figure 1. Pin Connections for TSOP
and STSOP Packages
1
LH52D1000
CMOS 1M (128K
×
8) Static RAM
A
0
A
1
A
2
A
3
20
19
18
17
16
10
1024
ROW
DECODER
MEMORY
CELL ARRAY
(1024 x 128 x 8)
8 V
CC
24 GND
A
4
A
5
15
A
6
14
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
13
3
2
31
1
12
4
11
7
10
ADDRESS
BUFFER
128 x 8
7
COLUMN
DECODER
128
COLUMN GATE
8
CE
CONTROL
LOGIC
CE
1
30
CE
2
6
WE 5
OE 32
OE, WE
CONTROL
LOGIC
I/O BUFFER
21 22 23 25 26 27 28 29
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
52D1000S-2
Figure 2. LH52D1000 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
– A
16
CE
1
CE
2
WE
OE
Address inputs
Chip enable 1
Chip enable 2
Write enable
Output enable
I/O
1
– I/O
8
V
CC
GND
NC
Data inputs and outputs
Power supply
Ground
No connection
2
CMOS 1M (128K
×
8) Static RAM
LH52D1000
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
– I/O
8
SUPPLY CURRENT
NOTE
H
L
L
L
L
H
H
H
L
H
H
L
H
Standby
Write
Read
Output disable
High
impedance
Data input
Data output
High
impedance
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
1
1
NOTE:
1.
= Don’t care
L = Low
H = High
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Input voltage
Operating temperature
Storage temperature
V
CC
V
IN
T
OPR
T
STG
-0.3 to +4.6
- 0.3 to V
CC
+ 0.3
-40 to +85
-55 to +1 50
V
V
°C
°C
1
1, 2
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
2. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED DC OPERATING CONDITIONS (T
A
= -40°C to +85°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
Input voltage
V
CC
V
IH
V
IL
2.7
2.0
–0.3
3.0
3.6
V
CC
+ 0.3
0.6
V
V
V
1
NOTE:
1. Undershoot of –3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICAL CHARACTERISTICS (T
A
= -25°C to +85°C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input
leakage
current
Output
leakage
current
Operating
supply
current
Standby
current
Output
voltage
I
LI
VIN = 0 to V
CC
CE
1
= V
IH
or CE
2
= V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= 0 V to V
CC
V
IN
= V
IL
or V
IH,
CE
1
= V
IL
, WE = V
IH
CE
2
= V
IH
, I
I/O
= 0 mA
CE
1
= 0.2 V, V
IN
= 0.2 V or V
CC
- 0.2 V
CE
2
, WE = V
CC
- 0.2 V, I
I/O
= 0 mA
CE
1
= V
CC
– 0.2 V or
CE
2
= 0.2 V
CE
1
= V
IH
or CE
2
= V
IL
I
OL
= 2.1 mA
I
OH
= –0.5 mA
t
CYCLE
= Min
t
CYCLE
= 1.0
µs
–1.0
1.0
µA
I
LO
I
CC
I
CC1
I
SB
I
SB1
V
OL
V
OH
–1.0
V
CC
- 0.5
1.0
40
µA
mA
6
45
2.0
0.4
µA
mA
V
V
3
LH52D1000
CMOS 1M (128K
×
8) Static RAM
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
MODE
NOTE
Input pulse level
Input rise and fall time
Input and output timing Ref. level
Output load
NOTE:
1. Including scope and jig capacitance.
0.4 V to 2.4 V
5 ns
1.5 V
100 pF + 1TTL
1
READ CYCLE (T
A
= -40°C to +85°C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
CE
1
access time
CE
2
access time
Output enable to output valid
Output hold from address change
CE
1
Low to output active
CE
2
High to output active
OE Low to output active
CE
1
High to output in High impedance
CE
2
Low to output in High impedance
OE High to output in High impedance
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
85
10
5
5
0
0
0
0
85
85
85
45
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
NOTE:
1. Active output to High impedance and High impedance to output active tests specified for a
±200
mV transition
from steady state levels into the test load.
WRITE CYCLE (T
A
= -40°C to +85°C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
CE
1
Low to end of write
CE
2
High to end of write
Address setup time
Write pulse width
Write recovery time
Input data setup time
Input data hold time
WE High to output active
WE Low to output in High impedance
OE High to output in High impedance
t
WC
t
CW1
t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
t
OHZ
85
75
75
0
60
0
35
0
0
0
0
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
NOTE:
1. Active output to High impedance and High impedance to output active tests specified for a
±200
mV transition
from steady state levels into the test load.
4
CMOS 1M (128K
×
8) Static RAM
LH52D1000
DATA RETENTION CHARACTERISTICS (T
A
= -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP
MAX.
UNIT
NOTE
Data retention
supply voltage
V
CCDR
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
V
CCDR
= 3.0 V
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
T
A
= 25°C
T
A
= 40°C
2.0
3.6
1.0
3.0
35
V
1
Data retention
supply current
I
CCDR
µA
1
Chip enable
setup time
Chip enable
hold time
t
CDR
0
ms
t
R
5
ms
NOTE:
1. CE
2
≥
V
CCDR
– 0.2 V or CE
2
≤
0.2 V
2. Typical values at T
A
= 25°C
PIN CAPACITANCE (T
A
= 25°C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
I/O capacitance
C
IN
C
I/O
V
IN
= 0 V
V
I/O
= 0 V
10
10
pF
pF
1
1
NOTE:
1. This parameter is sampled and not production tested.
5
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