LH28F004SU-Z9
FEATURES
42-PIN CSP
4M (512 × 8) Flash Memory
TOP VIEW
•
512K × 8 Word Configuration
•
2.7 V Write/Erase Operation (5 V ± 0.5 V
V
PP
, 3.0 V ± 0.3 V V
CC
, +15°C to +35°C)
– No Requirement For DC/DC Converter
To Write/Erase
1
A GND
B
C
D
E
F
A
17
A
10
A
14
A
16
A
15
2
DQ
6
DQ
7
NC
A
13
A
11
A
12
3
V
CC
DQ
4
DQ
5
A
9
WE
A
8
4
V
CC
NC
NC
NC
RP
V
PP
5
DQ
2
NC
DQ
3
RY/BY
A
7
A
18
6
OE
DQ
0
DQ
1
A
6
A
4
A
5
7
GND
CE
A
0
A
3
A
1
A
2
•
150 ns Maximum Access Time
(V
CC
= 3.3 V ± 0.3 V)
•
Minimum 2.7 V Read Capability
– 190 ns Maximum Access Time
(V
CC
= 2.7 V, -20°C to +85°C)
– 180 ns Maximum Access Time
(V
CC
= 2.7 V, 0°C to +70°C)
•
32 Independently Lockable Blocks (16K)
•
100,000 Erase Cycles per Block
•
Automated Byte Write/Block Erase
– Command User Interface
– Status Register
– RY
/BY
»
Status Output
»
28F004SU-Z9-1
Figure 1. CSP Configuration
INTRODUCTION
Sharp’s LH28F004SU 4M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write
performance, the LH28F004SU is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F004SU’s independently lockable 32 sym-
metrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F004SU’s 5.0 V/3.3 V power supply operation
enables the design of memory cards which can be read
in 3.3 V system and written in 5.0 V/3.3 V systems. Its
x8 architecture allows the optimization of memory to
processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp’s 0.45 µm ETOX™ process technology, the
LH28F004SU is the most cost-effective, high-density
3.3 V flash memory.
•
System Performance Enhancement
– Erase Suspend For Read
– Two-Byte Write
– Full Chip Erase
•
Data Protection
– Hardware Erase/Write Lockout During
Power Transitions
– Software Erase/Write Lockout
•
Independently Lockable For Write/Erase
On Each Block (Lock Block and Protect
Set/Reset)
•
4 µA (Typ.) I
CC
In CMOS Standby
•
0.2 µA (Typ.) Deep Power-Down
•
State-of-the-Art 0.45 µm ETOX™
Flash Technology
•
Extended Temperature Operation
– -20°C to +85°C (Read)
– +15°C to +35°C (Write/Erase)
•
42-pin, 0.67 mm × 8 mm × 8 mm
CSP Package
1
LH28F004SU-Z9
4M (512K × 8) Flash Memory
DQ
0
- DQ
7
OUTPUT
BUFFER
INPUT
BUFFER
ID
REGISTER
DATA
QUEUE
REGISTERS
I/O
LOGIC
OUTPUT
MULTIPLEXER
CSR
REGISTER
ESRs
CUI
CE
OE
WE
RP
DATA
COMPARATOR
A
0
- A
18
INPUT
BUFFER
Y-DECODER
Y GATING/SENSING
16KB BLOCK 30
16KB BLOCK 31
16KB BLOCK 0
16KB BLOCK 1
WSM
RY/BY
ADDRESS
QUEUE
LATCHES
...
X-DECODER
...
ADDRESS
COUNTER
...
PROGRAM/
ERASE
VOLTAGE
SWITCH
V
PP
V
CC
GND
28F004SU-Z9-2
Figure 2. LH28F004SU-Z9 Block Diagram
2
4M (512K × 8) Flash Memory
LH28F004SU-Z9
PIN DESCRIPTIONS
SYMBOL
TYPE
NAME AND FUNCTION
WORD-SELECT ADDRESSES:
Select a word within one 16K block. These addresses
are latched during Data Writes.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DATA INPUT/OUTPUT:
Inputs data and commands during CUI write cycles. Outputs
array, buffer, identifier or status data in the appropriate Read mode. Floated when the
chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS:
Activate the device’s control logic, input buffers, decoders and
sense amplifiers. CE
»
must be low to select the device.
RESET/POWER-DOWN:
With RP
»
low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is turned
on, RP
»
pin is turned to low in order to return the device to default configuration. When
the power transition has occurred, or the power on/ off ,RP
»
is required to stay low in
order to protect data from noise. When returning from Deep Power-Down, a recovery
time of 750 ns is required to allow these circuits to power-up. When RP
»
goes low, any
current or pending WSM operation(s) are terminated, and the device is reset. All
Status registers return to ready (with all status flags cleared). After returning, the
device is in read array mode.
OUTPUT ENABLE:
Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
»
is high.
WRITE ENABLE:
Controls access to the CUI, Data Queue Registers and Address Queue
Latches. WE is active low, and latches both address and data (command or array) on
its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it indicates that the WSM
is busy performing an operation. When the WSM is ready for new operation or Erase is
Suspended, or the device is in deep power-down mode RY
»
/BY
»
pin is floated.
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):
For erasing memory array blocks or
writing words/bytes into the flash array.
DEVICE POWER SUPPLY (READ 2.7 V ~ 3.6 V,WRITE/ERASE 2.7 V ~ 3.3 V):
Do not
leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating
A
0
- A
13
A
14
- A
18
INPUT
INPUT
DQ
0
- DQ
7
INPUT/OUTPUT
CE
»
INPUT
RP
»
INPUT
OE
»
INPUT
WE
INPUT
RY
»
/BY
»
OPEN DRAIN
OUTPUT
SUPPLY
SUPPLY
SUPPLY
V
PP
V
CC
GND
NC
DESCRIPTION
The LH28F004SU is a high performance 4M
(4,194,304 bit) block erasable non-volatile random ac-
cess memory organized as 512K × 8. The LH28F004SU
includes thirty-two 16K (16,384) blocks. A chip memory
map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F004SU:
•
3 V Read, 5 V Write/Erase Operation
(5 V V
PP
, 2.7 V V
CC
)
•
Low Power Capability
(2.7 V V
CC
Read and Write/Erase)
•
Improved Write Performance
•
Dedicated Block Write/Erase Protection
•
Command-Controlled Memory Protection
Set/Reset Capability
3
LH28F004SU-Z9
4M (512K × 8) Flash Memory
MEMORY MAP
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
28F004SU-Z9-3
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash Memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Serial Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
20 µs. A Block Erase operation erases one of the 32
blocks in typically 0.8 seconds independent of the other
blocks.
LH28F004SU allows to erase all unlocked blocks. It
is desirable in case of which you have to implement
Erase operation maximum 32 times.
LH28F004SU enables Two-Byte serial Write which
is operated by three times command input. Writing of
memory data is performed typically within 30 µs per
two-byte. This feature can improve system write perfor-
mance by up to typically 15 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY
»
/BY
»
output pin provide informa-
tion on the progress of the requested operation.
Same as the LF28F008SA, LH28F004SU requires
an operation to complete before the next operation can
be requested, also it allows to suspend block erase to
read data from any other block, and allow to resume
erase operation.
The LH28F004SU provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F004SU has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
When the device power-up or RP
»
turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single block
Erase. Write Protect Set/Confirm command must be writ-
ten to reflect the actual lock status . However, when the
device power-on or RP
»
turns High, Erase All Unlocked
Blocks can be used. If used, Erase is performed with
reflecting actual lock status, and after that Write and
Block Erase can be used.
Figure 3. Memory Map (Byte-Wide Mode)
The LH28F004SU is available in a 42-pin, 0.67 mm
thick × 8 mm × 8 mm CSP package. This form factor
and pinout allow for very high board layout densities.
A Command User Interface (CUI) serves as the
system interface between the microprocessor or micro-
controller and the internal memory operation.
4
4M (512K × 8) Flash Memory
LH28F004SU-Z9
The LH28F004SU contains a Compatible Status
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register. This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F004SU from a
LH28F008SA based design.
The LH28F004SU incorporates an open drain
RY
»
/BY
»
output pin. This feature allows the user to or-tie
many RY
»
/BY
»
pins together in a multiple memory con-
figuration such as a Resident Flash Array.
The LH28F004SU is specified for a maximum
access time of 150 ns (t
ACC
) at 3.3 V operation (3.0 to
3.6 V) over the commercial temperature range (-20 to
+85°C). A corresponding maximum access time of
190 ns (t
ACC
) at 2.7 V (-20 to +85°C) and 180 ns (t
ACC
)
at 2.7 V (0 to +70°C) is achieved for reduced power
consumption applications.
The LH28F004SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical I
CC
current is 1 mA at 3.3 V.
A Deep Power-Down mode of operation in invoked
when the RP
»
(called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode. This mode
brings the device power consumption to less than 8 µa,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP
»
pin is turned to low in order to
return the device to default configuration. When the
power transition has occurred, or at the power on/off,
RP
»
is required to stay low in order to protect data from
noise. A recovery time of 750 ns is required from RP
»
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current op-
eration will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE
»
transitions high and RP
»
stays high with all input
control pins at CMOS levels. In this mode, the device
draws an I
CC
standby current of 15 µA.
BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS
Bus Operations
MODE
RP
»
CE
»
OE
»
WE
A
0
DQ
0-7
RY
»
/BY
»
NOTE
Read
Output Disable
Standby
Deep Power-Down
Manufacturer ID
Device ID
Write
V
IH
V
IH
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
X
V
IL
V
IL
V
IL
V
IL
V
IH
X
X
V
IL
V
IL
V
IH
V
IH
V
IH
X
X
V
IH
V
IH
V
IL
X
X
X
X
V
IL
V
IH
X
D
OUT
High-Z
High-Z
High-Z
B0H
ID
D
IN
X
X
X
V
OH
V
OH
V
OH
X
1, 2, 7
1, 6, 7
1, 6, 7
1, 3
4
4
1, 5, 6
NOTES:
1. X can be V
IH
or V
IL
for address or control pins except for RY
»
/BY
»
, which is either V
OL
or V
OH
.
2. RY
»
/BY
»
output is open drain. When the WSM is ready, Erase is suspended or the device is in deep
power-down mode, RY
»
/BY
»
will be at V
OH
if it is tied to V
CC
through a resistor. When the RY
»
/BY
»
at V
OL
is independent of OE
»
while a WSM operation is in progress.
3. RP
»
at GND ± 0.2 V ensures the lowest deep power-down current.
4. A
0
at V
IL
provide manufacturer ID codes. A
0
at V
IH
provide device ID codes. Device ID code= 23H.
All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations, and Lock-Block operations can only
be successfully completed when V
PP
= VPPH.
6. While the WSM is running, RY
»
/BY
»
in Level-Mode (default) stays at V
OL
until all operations are complete.
RY
»
/BY
»
goes to V
OH
when the WSM is not busy or in erase suspend mode.
7. RY
»
/BY
may be at V
OL
while the WSM is busy performing various operations. For example, a status register
read during a write operation.
5
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