DA7212
Ultra-low power stereo codec
Company confidential
General description
The DA7212 is an ultra-low power audio codec targeting portable audio devices. The input paths
support stereo FM line input and up to four analogue (or two analogue and two digital) microphones
with two independent microphone biases. Comprehensive analogue mixing and bypass paths to the
output drivers are available.
The headphone output is true-ground Class G with integrated charge pump. There is also a
differential Class AB speaker driver that can serve as a mono lineout.
Digital audio transfer to/from the external processor is via a bi-directional digital audio interface that
supports all common sample rates and formats. The device may be operated in slave or master
modes using the internal PLL which may be bypassed if not required.
To fully optimise each customer application, a range of built in filtering, equalisation and audio
enhancements are available. These are accessible by the processor over the I2C serial interface.
Key features
■
100 dB SNR stereo audio playback into 16 Ω
■
Built-in 5-band equaliser, ALC and noise-gate
headphones
functions
Built-in beep generator
Integrated system controller to eliminate pops
and clicks
Minimised external component count
34-ball WL-CSP (4.54 mm x 1.66 mm)
package
Staggered 0.5 mm pitch for easy PCB routing
allowing low cost manufacture
■
3.1 mW power consumption for stereo DAC to
■
headphone playback
■
■
1.2 W mono speaker driver
■
650 µW mono voice record
■
■
Stereo digital microphone support
■
■
Supports up to four analogue microphones
■
■
Two low-noise microphone-bias outputs
■
Low-power PLL provides system clocking and
audio sample rate flexibility
Applications
■
Personal Media Players
■
Audio headphone/headsets
■
Wearables
■
Embedded applications
■
Arduino compatible development systems
Figure 1: The DA7212 chip
Datasheet
Revision 3c
1 of 129
24-Nov-2015
© 2015 Dialog Semiconductor
DA7212
Ultra-low power stereo codec
Company confidential
Contents
General description ............................................................................................................................. 1
Key features ......................................................................................................................................... 1
Applications ......................................................................................................................................... 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 4
Tables ................................................................................................................................................... 5
1
2
3
4
5
6
7
8
9
Terms and definitions ................................................................................................................... 7
Block diagram ................................................................................................................................ 8
Pinout ............................................................................................................................................. 9
Absolute maximum ratings ........................................................................................................ 11
Recommended operating conditions ........................................................................................ 11
Electrical characteristics ............................................................................................................ 12
Parametric specifications ........................................................................................................... 13
Digital signal processing ............................................................................................................ 16
Audio outputs .............................................................................................................................. 18
10 Clock generation ......................................................................................................................... 22
11 Phase locked loop (PLL) ............................................................................................................. 22
12 Digital interfaces ......................................................................................................................... 23
12.1 Codec start-up time ............................................................................................................. 26
13 Functional description ................................................................................................................ 27
13.1 General description ............................................................................................................. 27
13.2 Input signal chain ................................................................................................................ 28
13.3 Microphone inputs ............................................................................................................... 29
13.4 Digital microphones ............................................................................................................. 29
13.5 Auxiliary inputs .................................................................................................................... 30
13.6 Input mixers ......................................................................................................................... 31
13.7 Stereo audio ADC ............................................................................................................... 31
13.8 Automatic level control (ALC) ............................................................................................. 32
13.9 Beep generator and controller ............................................................................................ 34
13.10 Output signal chain ............................................................................................................. 35
13.11 Stereo audio DAC ............................................................................................................... 35
13.12 Output mixer ........................................................................................................................ 36
13.13 Headphone amplifier ........................................................................................................... 36
13.14 Speaker amplifier ................................................................................................................ 37
13.15 Charge pump control........................................................................................................... 37
13.16 Charge pump clock control ................................................................................................. 39
13.17 Boosting the charge pump using demand feedback control ............................................... 39
13.17.1 Tracking the demands on the charge pump output ............................................. 39
13.17.1.1 CP_MCHANGE = 00 (manual mode) .............................................. 39
13.17.1.2 CP_MCHANGE = 01 (tracking the PGA gain setting) ..................... 39
13.17.1.3 CP_MCHANGE = 10 (tracking the DAC signal setting) .................. 39
13.17.1.4 CP_MCHANGE = 11 (tracking the output signal magnitude) .......... 39
Datasheet
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© 2015 Dialog Semiconductor
DA7212
Ultra-low power stereo codec
Company confidential
13.18
13.19
13.20
13.21
13.22
13.23
13.24
13.25
13.26
13.27
13.28
13.29
13.30
13.31
13.32
13.33
13.34
13.35
13.36
13.37
13.38
13.39
13.40
13.17.2 Specifying clock frequencies when tracking the charge pump output demand... 40
13.17.3 Controlling the boost of the charge pump clock-frequency ................................. 40
13.17.3.1 CP_ANALOGUE_LVL = 01 ............................................................. 40
13.17.3.2 CP_ANALOGUE_LVL = 10 ............................................................. 40
Other charge pump controls ............................................................................................... 41
Digital signal processing engine ......................................................................................... 42
Variable high-pass audio filter (DC Cut) ............................................................................. 42
Variable high pass filter (wind noise filtering) ..................................................................... 43
DAC 5-band equaliser ......................................................................................................... 44
Soft mute ............................................................................................................................. 46
Playback noise-gate ............................................................................................................ 46
Clock modes ....................................................................................................................... 47
PLL bypass mode ............................................................................................................... 48
13.26.1 Normal PLL mode (DAI master) .......................................................................... 49
13.26.2 Example calculation of the feedback divider setting: ........................................... 50
SRM PLL mode (DAI slave) ................................................................................................ 51
32 kHz PLL mode (DAI master) .......................................................................................... 51
Operating with a 2 MHz to 5 MHz MCLK ............................................................................ 51
Mixed sample rates ............................................................................................................. 51
I2C control interface ............................................................................................................ 52
Details of the I2C control interface protocol ........................................................................ 53
Digital audio interface (DAI) ................................................................................................ 55
I2S mode ............................................................................................................................. 56
Left justified mode ............................................................................................................... 56
Right justified mode ............................................................................................................. 56
DSP mode ........................................................................................................................... 57
Time division multiplexing (TDM) mode .............................................................................. 58
13.38.1 Configuration of the digital audio interface .......................................................... 59
Pop-free and click-free start-up using the system controllers ............................................. 59
13.39.1 Level 1 system controller (SCL1) ........................................................................ 59
13.39.2 Level 2 system controller (SCL2) ........................................................................ 60
Power supply – standby mode ............................................................................................ 60
13.40.1 Entering standby mode ........................................................................................ 60
13.40.2 Exiting standby mode .......................................................................................... 60
14 Register definitions ..................................................................................................................... 61
14.1 Register map ....................................................................................................................... 61
14.2 Status registers ................................................................................................................... 67
14.3 System initialisation registers .............................................................................................. 72
14.4 Input gain/select filter registers ........................................................................................... 78
14.5 Output gain-filter registers ................................................................................................... 83
14.6 System controller registers.................................................................................................. 91
14.7 Control registers .................................................................................................................. 93
14.8 Mixed sample mode registers ........................................................................................... 102
14.9 Configuration registers ...................................................................................................... 103
15 Package information ................................................................................................................. 118
15.1 Package outlines ............................................................................................................... 118
15.2 Soldering information ........................................................................................................ 119
Datasheet
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© 2015 Dialog Semiconductor
DA7212
Ultra-low power stereo codec
Company confidential
16 Ordering information ................................................................................................................ 119
Appendix A Applications information ........................................................................................... 120
A.1 Codec initialisation ............................................................................................................ 120
A.2 Automatic ALC calibration ................................................................................................. 120
A.3 Troubleshooting ................................................................................................................ 121
Appendix B Components ................................................................................................................ 122
B.1 Audio inputs ...................................................................................................................... 122
B.2 Microphone bias ................................................................................................................ 123
B.3 Digital microphone ............................................................................................................ 123
B.4 Audio outputs .................................................................................................................... 123
B.5 Headphone charge pump ................................................................................................. 124
B.6 Digital interfaces ................................................................................................................ 125
B.7 References ........................................................................................................................ 126
B.8 Supplies ............................................................................................................................ 126
B.9 Ground .............................................................................................................................. 127
B.10 Capacitor selection ............................................................................................................ 127
Appendix C PCB layout guidelines ............................................................................................... 128
C.1 Layout and schematic support .......................................................................................... 128
C.2 General recommendations ................................................................................................ 128
Figures
Figure 1: The DA7212 chip.................................................................................................................... 1
Figure 2: Block diagram showing component values for a typical application ...................................... 8
Figure 3: DA7212 ball layout ................................................................................................................. 9
Figure 4: I2C bus timing ...................................................................................................................... 24
Figure 5: Digital audio interface timing diagram .................................................................................. 25
Figure 6: Audio input routing and gain ranges .................................................................................... 28
Figure 7: Typical microphone application for MIC1 (MIC2 is similar) .................................................. 29
Figure 8: Digital microphone timing example ...................................................................................... 30
Figure 9: Principle of operation of the ALC ......................................................................................... 32
Figure 10: Attack, delay and hold parameters..................................................................................... 33
Figure 11: Analogue output signal paths and gain ranges .................................................................. 35
Figure 12: Input (clk) and output clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010 .................. 39
Figure 13: ADC and DAC DC blocking (Cut-off frequency setting ‘00’ to ‘11’, 16 kHz) ...................... 42
Figure 14: Wind noise high-pass filter (cut-off frequency setting ‘000’ to ‘111’, 16 kHz) .................... 43
Figure 15: Equaliser filter band 1 frequency response at FS = 48 kHz............................................... 44
Figure 16: Equaliser filter band 2 frequency response at FS = 48 kHz............................................... 45
Figure 17: Equaliser filter band 3 frequency response at FS = 48 kHz............................................... 45
Figure 18: Equaliser filter band 4 frequency response at FS = 48 kHz............................................... 45
Figure 19: Equaliser filter band 5 frequency response at FS = 48 kHz............................................... 46
Figure 20: Schematic of the I2C control interface bus ........................................................................ 52
Figure 21 Timing of I2C START and STOP conditions ....................................................................... 53
Figure 22: I2C byte write (SDA signal) ................................................................................................ 53
Figure 23: Examples of the I2C byte read (SDA line) ......................................................................... 53
Figure 24: Examples of I2C page read (SDA line) .............................................................................. 54
Figure 25: I2C page write (SDA line) ................................................................................................... 54
Figure 26: I2C repeated write (SDA line) ............................................................................................ 54
Figure 27: Master mode (DAI_CLK_EN = 1) ....................................................................................... 55
Figure 28: Slave mode (DAI_CLK_EN = 0) ......................................................................................... 55
Figure 29: I2S mode ............................................................................................................................ 56
Figure 30: Left justified mode .............................................................................................................. 56
Datasheet
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DA7212
Ultra-low power stereo codec
Company confidential
Figure 31: Right justified mode ............................................................................................................ 56
Figure 32: DSP mode .......................................................................................................................... 57
Figure 33: TDM example (slave mode) ............................................................................................... 58
Figure 34: TDM mode (left justified mode) .......................................................................................... 58
Figure 35: DA7212 package outline drawing .................................................................................... 118
Figure 36: MICBIAS decoupling ........................................................................................................ 123
Figure 37: Recommended headphone layout ................................................................................... 123
Figure 38: Charge pump decoupling ................................................................................................. 124
Figure 39: Charge pump flying capacitor .......................................................................................... 124
Figure 40: I2C pull ups ...................................................................................................................... 125
Figure 41: Reference capacitors ....................................................................................................... 126
Figure 42: Power supply decoupling ................................................................................................. 126
Figure 43: Example layout ................................................................................................................. 128
Tables
Table 1: Pin descriptions ....................................................................................................................... 9
Table 2: Pin type definition .................................................................................................................. 10
Table 3: Absolute maximum ratings .................................................................................................... 11
Table 4: Recommended operating conditions ..................................................................................... 11
Table 5: Power consumption ............................................................................................................... 12
Table 6: Reference voltage generation ............................................................................................... 12
Table 7: Analogue to digital converter (ADC) ...................................................................................... 13
Table 8: Microphone bias .................................................................................................................... 14
Table 9: Input mixing units................................................................................................................... 15
Table 10: ADC/DAC digital high-pass filter cut-off frequencies in music mode .................................. 16
Table 11: ADC/DAC Digital high-pass filter cut-off frequencies in voice mode ................................... 16
Table 12: DAC 5-band equaliser frequencies ..................................................................................... 17
Table 13: Beep generator .................................................................................................................... 17
Table 14: Digital to analogue converter (DAC) ................................................................................... 18
Table 15: Class AB lineout amplifier / speaker.................................................................................... 19
Table 16: True ground charge pump ................................................................................................... 20
Table 17: True ground headphone amplifier ....................................................................................... 21
Table 18: MCLK input .......................................................................................................................... 22
Table 19: PLL mode ............................................................................................................................ 22
Table 20: Bypass mode ....................................................................................................................... 22
Table 21: I/O characteristics ................................................................................................................ 23
Table 22: I2C control bus (VDD_IO = 1.8 V) ....................................................................................... 24
Table 23: Digital audio interface timing (I2S/DSP in master/slave mode) .......................................... 25
Table 24: Codec start-up times ........................................................................................................... 26
Table 25: DTMF keypad frequencies .................................................................................................. 34
Table 26: Charge pump output voltage control ................................................................................... 37
Table 27: CP_THRESH_VDD2 settings in DAC_VOL mode (CP_MCHANGE = 10) ......................... 38
Table 28: CP_THRESH_VDD2 settings in signal size mode (CP_MCHANGE = 11) ......................... 38
Table 29: Charge pump current load control ....................................................................................... 41
Table 30: ADC/DAC digital high-pass filter specifications in audio mode ........................................... 42
Table 31: Wind noise high-pass filter specifications ........................................................................... 43
Table 32: DAC 5-band equaliser turnover/centre frequencies ............................................................ 44
Table 33: PLL clock modes ................................................................................................................. 47
Table 34: Sample rate control register and corresponding system clock frequency........................... 48
Table 35: PLL input divider .................................................................................................................. 49
Table 36: Example PLL configurations ................................................................................................ 50
Table 37: Ordering information .......................................................................................................... 119
Table 38: Offset calibration, MIC1_P and MIC2_P single ended, slave mode ................................. 121
Table 39: Audio inputs ....................................................................................................................... 122
Table 40: Microphone bias ................................................................................................................ 123
Table 41: Digital microphones ........................................................................................................... 123
Table 42: Headphone outputs ........................................................................................................... 123
Datasheet
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24-Nov-2015
© 2015 Dialog Semiconductor
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