LFECP3E-3F672I datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Programmable logic devices> LFECP3E-3F672I

LFECP3E-3F672I: DescriptionFPGA, 768 CLBS, 420 MHz, PQFP144; Categorysemiconductor Programmable logic devices; File Size480KB，117 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

Download Datasheet Parametric View All

LFECP3E-3F672I Overview

FPGA, 768 CLBS, 420 MHz, PQFP144

LFECP3E-3F672I Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	1.26 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	20 X 20 MM, TQFP-144
state	DISCONTINUED
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	OTHER
organize	768 CLBS
Maximum FCLK clock frequency	420 MHz
Number of configurable logic modules	768
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
The maximum delay of a CLB module	0.4000 ns

Preview

Download Datasheet

View All

LatticeECP/EC Family Data Sheet

Version 01.3

LatticeECP/EC Family Data S

Archite

November 2004

Preliminary

Architecture Overview

The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by P

ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded

(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DS

shown in Figure 2-2.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Fun

without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and re

tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and

are optimized for ﬂexibility allowing complex designs to be implemented quickly and efﬁciently. Logic

arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used

side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks

three rows of PFF blocks there is a row of PFU blocks.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on

right edges of the device can be conﬁgured as LVDS transmit/receive pairs. sysMEM EBRs are large de

memory blocks. They can be conﬁgured as RAM or ROM.

The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns a

Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. Th

route software tool automatically allocates these routing resources.

At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Bl

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relation

clocks. The LatticeECP/EC architecture provides up to four PLLs per device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sys

port which allows for serial or parallel device conﬁguration. The LatticeECP/EC devices use 1.2V as the

age.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change

www.latticesemi.com

2-1

Arch

Recommended Resources

Audio vibration thawing circuit diagram

Automatic electric oven circuit

Basic application circuit diagram of MAX743

Control tone generator

LA4190 power amplifier circuit

KA2309 (toy) radio remote control receiving control and regulating circuit

C Language Manual: Shared C language manual, hoping to bring useful content to others...; liuyy0928 DSP and ARM Processors

Principle of six-wire resistance measurement: I am a novice, and I have just started working on this kind of thing. I always can't find the principle of six-wire measurement. Can someone who has done it tell me about its principle and implementat...; 春风维修 Embedded System

desolate: RT...; fancunu Embedded System

The most effective way to learn electronics: The most effective method for learning electronics People spend the longest time using self-study methods in their lives. Reading books and doing things by yourself are self-study methods. 1. Have the...; wydz123 Analog electronics

A well-known MCU foreign company in Shanghai needs an automated test development engineer: Forwarded on behalf of a friend: Senior Engineer of Automated TestingJob Responsibilities:Responsible for developing automated testing tool software for testing embedded systemsResponsible product: MC...; maggiemamaqiao Recruitment

Defective soldering problems when soldering SMD products: [hide]Tombstone effectDue to the different amounts of solder paste, the tensile forces generated during the shrinkage process are different due to the effects of thermal expansion and contraction duri...; 探路者 LED Zone

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components