LFEC40E-5F256C datasheet, PDF - EEWORLD Datasheet

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LFEC40E-5F256C: DescriptionFPGA, 768 CLBS, 420 MHz, PQFP144; Categorysemiconductor Programmable logic devices; File Size480KB，117 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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LFEC40E-5F256C Overview

FPGA, 768 CLBS, 420 MHz, PQFP144

LFEC40E-5F256C Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	1.26 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	20 X 20 MM, TQFP-144
state	DISCONTINUED
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	OTHER
organize	768 CLBS
Maximum FCLK clock frequency	420 MHz
Number of configurable logic modules	768
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
The maximum delay of a CLB module	0.4000 ns

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LatticeECP/EC Family Data Sheet

Version 01.3

LatticeECP/EC Family Data S

Archite

November 2004

Preliminary

Architecture Overview

The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by P

ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded

(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DS

shown in Figure 2-2.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Fun

without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and re

tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and

are optimized for ﬂexibility allowing complex designs to be implemented quickly and efﬁciently. Logic

arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used

side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks

three rows of PFF blocks there is a row of PFU blocks.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on

right edges of the device can be conﬁgured as LVDS transmit/receive pairs. sysMEM EBRs are large de

memory blocks. They can be conﬁgured as RAM or ROM.

The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns a

Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. Th

route software tool automatically allocates these routing resources.

At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Bl

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relation

clocks. The LatticeECP/EC architecture provides up to four PLLs per device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sys

port which allows for serial or parallel device conﬁguration. The LatticeECP/EC devices use 1.2V as the

age.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change

www.latticesemi.com

2-1

Arch

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