Data Sheet
FEATURES
SFP reference design available
Input sensitivity: 3 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 2 mV to 13 mV
Rx signal strength indicator (RSSI):
SFF-8472 compliant average power measurement
Single-supply operation: 3.3 V
Low power dissipation: 130 mW
Available in space-saving 3 mm × 3 mm 16-lead LFCSP
3.3 V 2.7 Gb/s
Limiting Amplifier
ADN2890
GENERAL DESCRIPTION
The
ADN2890
is a high gain, limiting amplifier optimized for
use in SONET, Gigabit Ethernet (GbE), and Fibre Channel
optical receivers that accept input levels of up to 2.0 V p-p
differential and have 3 mV p-p differential input sensitivity. The
ADN2890
provides the receiver functions of quantization and
loss of signal (LOS) detection. The
ADN2890
can easily operate
at up to 3.2 Gb/s to support LX4 transceivers.
The limiting amplifier also measures average received power
based on a direct measurement of the photodiode current with
better than 1 dB of accuracy over the entire input range of the
receiver. This eliminates the need for external average Rx power
detection circuitry in SFF-8472 compliant optical transceivers.
The
ADN2890
limiting amplifier operates from a single 3.3 V
supply, has low power dissipation, and is available in a space-
saving 3 mm × 3 mm 16-lead lead frame chip scale package
(LFCSP).
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/12/48, GbE, Fibre Channel receivers
10GBASE-LX4 transceivers
WDM transponders
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVEE
DRVCC
DRVCC
50Ω
50Ω
OUTP
OUTN
50Ω
50Ω
3kΩ
V
REF
RSSI/LOS
DETECTOR
CAZ1
0.01
µ
F
CAZ2
LOS
+V
10k
Ω
DRVEE
ADN2890
C
F
R
F
PIN
ADN2880
NIN
PD_VCC
PD_CATHODE
RSSI_OUT
ADuC7020
Figure 1.
Rev. B
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04509-0-001
THRADJ SQUELCH
ADN2890
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Data Sheet
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................8
LIMAMP ........................................................................................8
Loss of Signal (LOS) Detector .....................................................8
Received Signal Strength Indicator (RSSI) ................................8
Squelch Mode ................................................................................8
Applications Information .................................................................9
PCB Design Guidelines ................................................................9
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changed CP-16-27 to CP-16-22.................................. Throughout
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
10/2013—Rev. 0 to Rev. A
Change to Output Voltage Swing Parameter, Table 1 .................. 3
Change to Figure 2 ........................................................................... 6
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
5/2004—Revision 0: Initial Version
Rev. B | Page 2 of 12
Data Sheet
SPECIFICATIONS
VCC = V
MIN
to V
MAX
, VEE = 0 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
QUANTIZER DC CHARACTERISTICS
Input Voltage Range
Input Common Mode
Peak-to-Peak Differential Input Range
Input Sensitivity
Input Offset Voltage
Input RMS Noise
Input Resistance
Input Capacitance
QUANTIZER AC CHARACTERISTICS
Input Data Rate
Small Signal Gain
S11
S22
Random Jitter
Deterministic Jitter
Low Frequency Cutoff
Power Supply Rejection
LOSS OF SIGNAL DETECTOR (LOS)
LOS Assert Level
Hysteresis
2.0
2.5
LOS Assert Time
LOS De-Assert Time
RSSI
Input Current Range
RSSI Output Accuracy
Gain
Offset
Compliance Voltage
POWER SUPPLIES
V
CC
I
CC
OPERATING TEMPERATURE RANGE
CML OUTPUT CHARACTERISTICS
Output Impedance
Output Voltage Swing
Output Rise and Fall Time
Min
1.8
2.1
4
3
100
235
50
0.65
2700
57
−10
−10
2.4
13.7
30
1.0
45
0.5
7.0
2.5
12.0
3.0
3.0
4.5
4.5
600
100
Typ
Max
2.8
2.7
2.0
Unit
V p-p
V
V p-p
mV p-p
µV
µV rms
Ω
pF
Mb/s
dB
dB
dB
ps rms
ps p-p
kHz
kHz
dB
mV p-p
mV p-p
dB
dB
dB
dB
ns
ns
µA
I
IN
≤ 20 µA
I
IN
> 20 µA
I
RSSI
/I
PD
At PD_CATHODE
ADN2890
Test Conditions/Comments
At PIN or NIN, dc-coupled
DC-coupled
PIN − NIN, ac-coupled
PIN − NIN, BER ≤ 1 × 10
−10
Single-ended
155
5
19
Differential
Differential, f < 2.7 GHz
Differential, f < 2.7 GHz
Input ≥ 10 mV p-p, OC-48, PRBS 2
23
− 1
Input ≥ 10 mV p-p, OC-48, PRBS 2
23
− 1
CAZ = Open
CAZ = 0.0 1 µF
100 kHz < f < 10 MHz
R
THRADJ
= 100 kΩ
R
THRADJ
= 0 Ω
OC-3, PRBS 2
23
− 1, R
THRADJ
= 0 Ω
OC-3, PRBS 2
23
− 1, R
THRADJ
= 10 kΩ
OC-48, PRBS 2
23
− 1, R
THRADJ
= 0 Ω
OC-48, PRBS 2
23
− 1, R
THRADJ
= 100 kΩ
DC-coupled
DC-coupled
4.0
16.0
6.0
7.5
5
1000
15%
10%
1.0
50
V
CC
− 1.05
3.0
−40
3.3
39
+25
50
700
80
V
CC
− 0.3
3.6
54
+85
mA/mA
nA
V
V
mA
°C
Ω
mV p-p
ps
T
MIN
to T
MAX
Single-ended
Differential
20% to 80%
650
800
100
Rev. B | Page 3 of 12
ADN2890
Parameter
LOGIC INPUTS (SQUELCH)
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
Input Current
LOGIC OUTPUTS (LOS)
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
Min
2.0
0.8
−100
100
2.4
0.4
Typ
Max
Unit
V
V
nA
nA
V
V
Data Sheet
Test Conditions/Comments
I
INH
, V
IN
= 2.4 V
I
INL
, V
IN
= 0.4 V
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to V
CC
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to V
CC
Rev. B | Page 4 of 12
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Storage Temperature
Operating Temperature Range
Lead Temperature Range (Soldering 10 s)
Junction Temperature
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
−65°C to +155°C
−40°C to +85°C
300°C
125°C
ADN2890
THERMAL RESISTANCE
θ
JA
is specified for 4-layer PCB with exposed paddle soldered
to GND.
Table 3.
Package Type
16-Lead 3 mm × 3 mm LFCSP
θ
JA
28
Unit
°C/W
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 5 of 12
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