LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
DESCRIPTION
The
LF3310
is a two-dimensional digital
image filter capable of filtering data at
real-time video rates. The device
contains both a horizontal and a
vertical filter which may be cascaded or
used concurrently for two-dimensional
filtering. The input, coefficient, and
output data are all 12-bits and in two’s
complement format.
The horizontal filter is designed to take
advantage of symmetric coefficient sets.
When symmetric coefficient sets are
used, the horizontal filter can be
configured as a 16-tap FIR filter. When
asymmetric coefficient sets are used, it
can be configured as an 8-tap FIR filter.
The vertical filter is an 8-tap FIR filter
with all required line buffers contained
on-chip. The line buffers can store
video lines with lengths from 4 to 3076
pixels.
Horizontal filter Interleave/Decima-
tion Registers (I/D Registers) and the
vertical filter line buffers allow
interleaved data to be fed directly into
the device and filtered without
separating the data into individual
data streams. The horizontal filter
can handle a maximum of sixteen
data sets interleaved together. The
vertical filter can handle interleaved
video lines which contain 3076 or less
data values. The I/D Registers and
horizontal accumulator facilitate
using decimation to increase the
number of filter taps in the horizontal
filter. Decimation of up to 16:1 is
supported.
The device has on-chip storage for 256
horizontal coefficient sets and 256
vertical coefficient sets. Each filter’s
coefficients are loaded independently
of each other allowing one filter’s
coefficients to be updated without
affecting the other filter’s coefficients.
In addition, a horizontal or vertical
coefficient set can be updated inde-
pendently from the other coefficient
sets in the same filter.
FEATURES
u
83 MHz Data Rate
u
12-bit Data and Coefficients
u
On-board Memory for 256 Horizontal
and Vertical Coefficient Sets
u
LF Interface
TM
Allows All 512
Coefficient Sets to be Updated
Within Vertical Blanking
u
Selectable 12-bit Data Output with
User-Defined Rounding and
Limiting
u
Seven 3K x 12-bit, Programmable
Two-Mode Line Buffers
u
16 Horizontal Filter Taps
u
8 Vertical Filter Taps
u
Two Operating Modes: Dimension-
ally Separate and Orthogonal
u
Supports Interleaved Data Streams
u
Horizontal Filter Supports Decima-
tion up to 16:1 for Increasing
Number of Filter Taps
u
3.3 Volt Power Supply
u
5 Volt Tolerant I/O
u
144 Lead PQFP
LF3310 B
LOCK
D
IAGRAM
12
DIN
11-0
16-TAP HORIZONTAL FILTER
256 COEFFICIENT SET STORAGE
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
8-TAP VERTICAL FILTER
256 COEFFICIENT SET STORAGE
12
3K LINE BUFFER
DOUT
11-0
Video Imaging Products
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11/08/2001-LDS.3310-H
I/D REGISTERS
F
IGURE
1.
E O I
DATA
REVERSAL
1-16
1-16
1-16
1-16
1-16
1-16
1-16
TXFR
DATA
DELAY
12
1-16
1-16
1-16
1-16
1-16
1-16
1-16
DEVICES INCORPORATED
12
ALU
13
ALU
13
ALU
13
ALU
13
ALU
13
ALU
13
ALU
13
ALU
13
A
B
A
B
A
B
A
B
A
B
A
B
A
B
1-16
A
DIN
11-0
B
HCF
11-0
HPAUSE
HLD
12
H Coef Bank 0
H Coef Bank 7
12
HORIZONTAL
LF
INTERFACE
12
VCF
11-0
VPAUSE
12
H Coef Bank 1
12
H Coef Bank 6
VLD
VERTICAL
LF
INTERFACE
CONFIGURATION AND
CONTROL REGISTERS
HCEN
12
12
H Coef Bank 5
H Coef Bank 2
8
HCA
7-0
VCEN
12
H Coef Bank 3
12
8
H Coef Bank 4
VCA
7-0
25
25
25
25
25
25
25
25
V Coef Bank 7
27
27
LF3310 F
UNCTIONAL
B
LOCK
D
IAGRAM
V Coef Bank 6
V Coef Bank 5
V Coef Bank 4
12
24
12
12
12
12
2
HACC
24
"0"
26
24
32
24
DATA
DELAY
24
32
24
26
24
"0"
32
32
4
HRSL
3-0
VERTICAL
ROUND
SELECT
LIMIT
HORIZONTAL
ROUND
SELECT
LIMIT
24
12
12
12
V Coef Bank 2
V Coef Bank 3
OE
4
VACC
VRSL
3-0
12
DOUT
11-0
12
3K Line Buffer
12
3K Line Buffer
12
3K Line Buffer
12
3K Line Buffer
12
3K Line Buffer
12
3K Line Buffer
12
3K Line Buffer
12
12
HSHEN
V Coef Bank 0
V Coef Bank 1
VSHEN
Horizontal / Vertical Digital Image Filter
Video Imaging Products
LF3310
11/08/2001-LDS.3310-H
CLK
LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
F
IGURE
2.
I
NPUT
F
ORMATS
Input Data
11 10 9
–2
11
2
10
2
9
(Sign)
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must
be connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
DIN
11-0
— Data Input
DIN
11-0
is the 12-bit registered data
input port. Data is latched on the
rising edge of CLK.
HCF
11-0
— Horizontal Coefficient Input
HCF
11-0
is used to load data into the
horizontal coefficient banks and the
Configuration/Control Registers.
Data present on HCF
11-0
is latched
into the Horizontal LF Interface
TM
on
the rising edge of CLK when HLD is
LOW (see the LF Interface
TM
section
for a full discussion).
HCA
7-0
— Horizontal Coefficient
Address
HCA
7-0
determines which row of data
in the horizontal coefficient banks is
fed to the multipliers in the horizontal
filter. HCA
7-0
is latched into the
Horizontal Coefficient Address
Register on the rising edge of CLK
when HCEN is LOW.
VCF
11-0
— Vertical Coefficient Input
VCF
11-0
is used to load data into the
vertical coefficient banks and the
Configuration/Control Registers.
Data present on VCF
11-0
is latched
into the Vertical LF Interface
TM
on the
rising edge of CLK when VLD is
LOW (see the LF Interface
TM
section
for a full discussion).
Coefficient Data
11 10 9
–2
0
2
–1
2
–2
(Sign)
2 1 0
2
2
2
1
2
0
2 1 0
2
–9
2
–10
2
–11
F
IGURE
3.
H
ORIZONTAL AND
V
ERTICAL
A
CCUMULATOR
F
ORMATS
Vertical Accumulator Output
31 30 29
–2
20
2
19
2
18
(Sign)
Horizontal Accumulator Output
31 30 29
–2
20
2
19
2
18
(Sign)
2 1 0
2
–9
2
–10
2
–11
2 1 0
2
–9
2
–10
2
–11
T
ABLE
1. O
UTPUT
F
ORMATS
SLCT
4-0
00000
00001
00010
S
11
S
10
F
11
F
10
S
9
F
9
F
12
F
11
F
10
F
13
F
12
F
11
···
···
···
···
S
6
F
6
F
7
F
8
S
5
F
5
F
6
F
7
···
···
···
···
S
2
F
2
F
3
F
4
S
1
F
1
F
2
F
3
S
0
F
0
F
1
F
2
·
·
·
10010
10011
10100
·
·
·
·
·
·
·
·
·
···
···
···
·
·
·
·
·
·
···
···
···
·
·
·
·
·
·
·
·
·
F
29
F
28
F
27
F
30
F
29
F
28
F
31
F
30
F
29
F
24
F
23
F
25
F
24
F
26
F
25
Controls
F
20
F
19
F
18
F
21
F
20
F
19
F
22
F
21
F
20
VCA
7-0
— Vertical Coefficient Address
VCA
7-0
determines which row of data
in the vertical coefficient banks is fed
to the multipliers in the vertical filter.
VCA
7-0
is latched into the Vertical
Coefficient Address Register on the
rising edge of CLK when VCEN is
LOW.
Outputs
DOUT
11-0
— Data Output
DOUT
11-0
is the 12-bit registered data
output port.
HLD — Horizontal Coefficient Load
When HLD is LOW, data on HCF
11-0
is latched into the Horizontal LF
Interface
TM
on the rising edge of CLK.
When HLD is HIGH, data can not be
latched into the Horizontal LF
Interface
TM
. When enabling the LF
Interface
TM
for data input, a HIGH to
LOW transition of HLD is required in
order for the input circuitry to func-
tion properly. Therefore, HLD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
TM
section for a full discussion).
Video Imaging Products
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11/08/2001-LDS.3310-H
LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
HACC — Horizontal Accumulator
Control
When HACC is HIGH, the horizontal
accumulator is enabled for accumula-
tion and the accumulator output
register is disabled for loading. When
HACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
HACC is latched on the rising edge of
CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical
accumulator is enabled for accumula-
tion and the accumulator output
register is disabled for loading. When
VACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
VACC is latched on the rising edge of
CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the
loading of data into the forward and
reverse I/D Registers in the horizon-
tal filter when the device is in Dimen-
sionally Separate Mode. If the device
is configured such that the horizontal
filter feeds the vertical filter, HSHEN
also enables or disables the loading of
data into the input register (DIN
11-0
).
If the device is configured such that
the vertical filter feeds the horizontal
filter and the vertical limit register is
under shift control, HSHEN also
enables or disables the loading of data
into the vertical limit register in the
vertical Round/Select/Limit circuitry.
In Orthogonal Mode, HSHEN also
enables or disables the loading of data
into the input register (DIN
11-0
) and
the line buffers in the vertical filter. It
is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable data loading. Both must
be active to enable data loading in
Orthogonal Mode. Also in Orthogo-
nal Mode, the horizontal and vertical
limit registers can not be disabled.
When HSHEN is LOW, data is loaded
into and shifted through the registers
HSHEN controls and the forward and
reverse I/D Registers on the rising
edge of CLK. When HSHEN is
HIGH, data is not loaded into or
shifted through the registers HSHEN
controls and the I/D Registers, and
their contents will not be changed.
HSHEN is latched on the rising edge
of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the
loading of data into the line buffers in
the vertical filter when the device is in
Dimensionally Separate Mode. If the
device is configured such that the
vertical filter feeds the horizontal
filter, VSHEN also enables or disables
the loading of data into the input
register (DIN
11-0
). If the device is
configured such that the horizontal
filter feeds the vertical filter and the
horizontal limit register is under shift
control, VSHEN also enables or
disables the loading of data into the
horizontal limit register in the hori-
zontal Round/Select/Limit circuitry.
In Orthogonal Mode, VSHEN also
enables or disables the loading of data
into the input register (DIN
11-0
) and
the forward and reverse I/D Registers
in the horizontal filter. It is important
to note that in Orthogonal Mode,
either HSHEN or VSHEN can disable
data loading. Both must be active to
enable data loading in Orthogonal
Mode. Also in Orthogonal Mode, the
horizontal and vertical limit registers
can not be disabled.
When VSHEN is LOW, data is loaded
into and shifted through the registers
VSHEN controls and the line buffers
on the rising edge of CLK. When
VSHEN is HIGH, data is not loaded
into or shifted through the registers
VSHEN controls and the line buffers,
and their contents will not be
changed. VSHEN is latched on the
rising edge of CLK.
HCEN — Horizontal Coefficient
Address Enable
When HCEN is LOW, data on HCA
7-0
is latched into the Horizontal Coeffi-
cient Address Register on the rising
edge of CLK. When HCEN is HIGH,
data on HCA
7-0
is not latched and the
register’s contents will not be
changed.
VLD — Vertical Coefficient Load
When VLD is LOW, data on VCF
11-0
is latched into the Vertical LF
Interface
TM
on the rising edge of CLK.
When VLD is HIGH, data can not be
latched into the Vertical LF
Interface
TM
. When enabling the LF
Interface
TM
for data input, a HIGH to
LOW transition of VLD is required in
order for the input circuitry to func-
tion properly. Therefore, VLD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
TM
section for a full discussion).
VCEN — Vertical Coefficient Address
Enable
When VCEN is LOW, data on VCA
7-0
is latched into the Vertical Coefficient
Address Register on the rising edge of
CLK. When VCEN is HIGH, data on
VCA
7-0
is not latched and the
register’s contents will not be
changed.
TXFR — Horizontal Filter LIFO
Transfer Control
TXFR is used to change which LIFO in
the data reversal circuitry sends data to
the reverse data path and which LIFO
receives data from the forward data
path. When TXFR goes LOW, the LIFO
sending data to the reverse data path
becomes the LIFO receiving data from
the forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
the reverse data path. The device must
see a HIGH to LOW transition of TXFR
in order to switch LIFOs.
Video Imaging Products
4
11/08/2001-LDS.3310-H
LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
F
IGURE
4.
D
IMENSIONALLY
S
EPARATE
M
ODE
: H
TO
V
12
DIN
11-0
HORIZONTAL FILTER
HRSL
3-0
— Horizontal Round/Select/
Limit Control
HRSL
3-0
determines which of the
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the horizontal Round/
Select/Limit circuitry (RSL circuitry).
A value of 0 on HRSL
3-0
selects
RSL register 0. A value of 1 selects
round/select/limit register 1 and so
on. HRSL
3-0
is latched on the rising
edge of CLK (see the horizontal
round, select, and limit sections for a
complete discussion).
VRSL
3-0
—Vertical Round/Select/Limit
Control
VRSL
3-0
determines which of the
sixteen user-programmable
RSL registers are used in the vertical
RSL circuitry. A value of 0 on
VRSL
3-0
selects RSL register 0. A
value of 1 selects RSL register 1 and
so on. VRSL
3-0
is latched on the rising
edge of CLK (see the vertical round,
select, and limit sections for a com-
plete discussion).
OE — Output Enable
When OE is LOW, DOUT
11-0
is
enabled for output. When OE is
HIGH, DOUT
11-0
is placed in a
high-impedance state.
HPAUSE — LF Interface
TM
Pause
When HPAUSE is HIGH, the Hori-
zontal LF Interface
TM
loading
sequence is halted until HPAUSE is
returned to a LOW state. This
effectively allows the user to load
coefficients and Control Registers at a
slower rate than the master clock (see
the LF Interface
TM
section for a full
discussion).
VPAUSE — LF Interface
TM
Pause
When VPAUSE is HIGH, the Vertical
LF Interface
TM
loading sequence is
halted until VPAUSE is returned to a
LOW state. This effectively allows the
user to load coefficients and Control
12
LINE BUFFER
LINE BUFFER
VERTICAL FILTER
LINE BUFFER
12
DOUT
11-0
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
F
IGURE
5.
12
DIN
11-0
D
IMENSIONALLY
S
EPARATE
M
ODE
: V
TO
H
LINE BUFFER
LINE BUFFER
LINE BUFFER
VERTICAL FILTER
12
HORIZONTAL FILTER
LINE BUFFER
LINE BUFFER
12
LINE BUFFER
LINE BUFFER
DOUT
11-0
Registers at a slower rate than the
master clock (see the LF Interface
TM
section for a full discussion).
OPERATIONAL MODES
Dimensionally Separate
In Dimensionally Separate Mode, the
horizontal and vertical filters are
cascaded together to form a
two-dimensional image filter (see
Figures 4 and 5). Bit 1 in Configura-
tion Register 4 determines the cascade
order. If this bit is set to “0”, data on
DIN
11-0
is fed into the horizontal filter
first. The horizontal filter then feeds
data into the vertical filter. If this bit
is set to “1”, data on DIN
11-0
is fed
into the vertical filter first. The
vertical filter then feeds data into the
horizontal filter.
Orthogonal
In Orthogonal Mode, the horizontal
and vertical filters are used concur-
rently to implement an orthogonal
kernel on the input data (see Figure 6).
Video Imaging Products
5
11/08/2001-LDS.3310-H
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