5962-9314302MYC datasheet, PDF

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5962-9314302MYC: DescriptionMicroprocessor, 32-Bit, 33MHz, CMOS, CQFP196, CERAMIC, QFP-196; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，38 Pages; ManufacturerThales Group

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5962-9314302MYC Overview

Microprocessor, 32-Bit, 33MHz, CMOS, CQFP196, CERAMIC, QFP-196

5962-9314302MYC Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	,
Contacts	196
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	33 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	NO
JESD-30 code	S-CQFP-G196
JESD-609 code	e4
Number of terminals	196
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Filter level	MIL-STD-883
speed	33 MHz
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	GULL WING
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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TS 68040

THIRD-GENERATION

32-BIT MICROPROCESSOR

DESCRIPTION

The TS 68040 is Thomson’s third generation of 68000-com-

patible, high-performance, 32-bit microprocessors. The

TS 68040 is a virtual memory microprocessor employing mul-

tiple, concurrent execution units and a highly integrated archi-

tecture to provide very high performance in a monolithic

HCMOS device. On a single chip, the TS 68040 integrates an

68030-compatible integer unit, an IEEE 754-compatible floa-

ting-point unit (FPU), and fully independent instruction and

data demand-paged memory management units (MMUs), in-

cluding independent 4K-byte instruction and data caches. A

high degree of instruction execution parallelism is achieved

through the use of multiple independent execution pipelines,

multiple internal buses, and a full internal Harvard architec-

ture, including separate physical caches for both instruction

and data accesses. The TS 68040 also directly supports ca-

che coherency in multimaster applications with dedicated on-

chip bus snooping logic.

The TS 68040 is user-object-code compatible with previous

members of the TS 68000 Family and is specifically opti-

mized to reduce the execution time of compiler-generated

code. The 68040 HCMOS technology, provides an ideal ba-

lance between speed, power, and physical device size.

Figure 1 is a simplified block diagram of the TS 68040. Ins-

truction execution is pipelined in both the integer unit and FPU.

Independent data and instruction MMUs control the main ca-

ches and the address translation caches (ATCs). The ATCs

speed up logical-to-physical address translations by storing re-

cently used translations. The bus snooper circuit ensures cache

coherency in multimaster and multiprocessing applications.

MAIN FEATURES

26-42 MIPS integer performance.

3.5-5.6 MFLOPS floating-point-performance.

IEEE 754-Compatible FPU.

Independant instruction and data MMUs.

4K-byte physical instruction cache and 4K-byte physical

data cache accessed simultaneously.

32-bit, nonmultiplexed external address and data buses

with synchronous interface.

User-object-code compatibility with all earlier TS 68000

microprocessors.

Multimaster / multiprocessor support via bus snooping.

Concurrent integer unit, FPU, MMU, bus controller, and

bus snooper maximize throughput.

4-Gbyte direct addressing range.

Software support including optimizing C compiler and

unix* system V port.

IEEE P 1149-1 test mode (J tag).

f = 25 MHz, 33 MHz ; V CC = 5 V

5 % ; PD = 7 W.

The use of the TS 88915T clock driver is suggested.

SCREENING

MIL-STD-883.

DESC. Drawing 5962-93143.

TCS standards.

R suffix

PGA 179

Ceramic Pin Grid Array

Cavity down

F suffix

CQFP 196

Gullwing shape lead Ceramic Quad Flat Pack

This document contains information on a new product. Specifica-

tions and information herein are subject to change without notice.

February 1998

1/38

TS 68040

A - GENERAL DESCRIPTION

Figure 1 :

Block diagram.

1 - INTRODUCTION

The TS 68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the

TS 68030 microprocessor with independent 4K-byte data and instruction caches and an on-chip FPU. The TS 68040 maintains

the 32-bit registers available with the entire TS 68000 Family as well as the 32-bit address and data paths, rich instruction

set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU

operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments.

The TS 68040 FPU is user-object-code compatible with the TS 68882 floating-point coprocessor and conforms to the

ANSI / IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly

used subset of the TS 68882 instruction set, and includes additional instruction formats for single and double-precision

rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit.

The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using

translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When

an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and

the physical address is supplied immediately, incurring no delay for adress translation. Each MMU has two transparent

translation registers available that define a one-to-one mapping for adress space segments ranging in size from 16 Mbytes

to 4 Gbytes each.

Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated

address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address

spaces protect the integrity of independent processes.

The instruction and data caches operate independently from the rest of the machine, storing information for fast access by

the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access

to both. The data cache provides writethrough or copyback write modes that can be configured on a page-by-page basis.

The TS 68040 bus controller supports a high-speed, nonmultiplexed, synchronous external bus interface, which allows the

following transfer sizes : byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using

burst transfers for both reads and writes to provide high data transfer rates.

3/38

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