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5962-9318705HXA

Description
Cache SRAM Module, 128KX32, 55ns, CMOS,
Categorystorage    storage   
File Size226KB,34 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
Download Datasheet Parametric View All

5962-9318705HXA Overview

Cache SRAM Module, 128KX32, 55ns, CMOS,

5962-9318705HXA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codeunknown
Maximum access time55 ns
I/O typeCOMMON
JESD-30 codeS-XHIP-P66
JESD-609 codee0
length30.1 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM MODULE
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeHIP
Encapsulate equivalent codePGA66,11X11
Package shapeSQUARE
Package formIN-LINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum seat height6.22 mm
Maximum standby current0.0116 A
Minimum standby current2 V
Maximum slew rate0.6 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb) - hot dipped
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationHEX
width30.1 mm
Base Number Matches1
REVISIONS
LTR
A
B
DESCRIPTION
Added device type 10. Redrew entire document.
Corrected true dimensioning table and removed dimensions A2 and F
in figure 1. Changed dimension A min from 0.185 inches to 0.180
inches for case outlines U and Y. Changes dimension A min from
0.210 inches to 0.200 inches for case outlines T and X. Added
vendor CAGE code 88379 for device types 01 through 10. Made
editorial changes throughout.
Added case outlines M, N, 4, and 5. Redrew entire document.
Table I, changed the maximum limit for the supply current 32-bit
mode test (I
CC32
) from 440 to 520 for device types 05 and 06, and
from 500 to 520 for device types 07 and 08. -sld
Figure 1: For case outlines 4 and 5 changed the dimension D3 min
and max limits to 1.020 and 1.060 inches. For case outlines 4 and 5
changed dimension A min limit to .135 inches. For case outlines 4
and 5 changed dimension L min limit to .132 inches. -sld
Table I; changed the max limit for I
CC32
for device types 05, 06, 07,
and 08 from 520 mA to 600 mA. Changed the max limit for I
CCDR1
for
device types 05 through 10 from 10.4 mA to 11.6 mA. -sld
Added device type 11. Added vendor CAGE 0EU86 for device types
05 through 09. -sld
Figure 1; changed the maximum limit for dimension D3 from 1.060
inches to 1.086 inches for case outlines 4 and 5. -sld
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Added footnote 3 for case outlines U, T, X, and Y on the
bulletin page. Redrew entire document. -sld
Added device types 12 through 18. -sld
Updated drawing. -gz
DATE (YR-MO-DA)
95-07-07
95-10-18
APPROVED
K. A. Cottongim
K. A. Cottongim
C
D
96-11-20
97-09-08
K. A. Cottongim
K. A. Cottongim
E
98-04-06
K. A. Cottongim
F
98-07-13
K. A. Cottongim
G
H
J
99-08-27
00-02-07
00-11-14
Raymond Monnin
Raymond Monnin
Raymond Monnin
K
L
01-11-13
07-04-16
Raymond Monnin
Robert M. Heber
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
L
15
L
16
L
17
L
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
L
19
L
20
L
21
L
1
L
22
L
2
L
23
L
3
L
24
L
4
L
25
L
5
L
26
L
6
L
7
L
8
L
9
L
10
L
11
L
12
L
13
L
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil/
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, DIGITAL, STATIC
RANDOM ACCESS MEMORY, CMOS, 128K x
32-BIT
DRAWING APPROVAL DATE
94-06-24
REVISION LEVEL
L
SIZE
A
SHEET
CAGE CODE
67268
1 OF
26
5962-93187
DSCC FORM 2233
APR 97
5962-E344-07

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