ICL8052/ICL7104,
ICL8068/ICL7104
August 1997
14-Bit/16-Bit, Microprocessor-
Compatible, 2-Chip, A/D Converter
Description
The ICL7104, combined with the ICL8052 or ICL8068,
forms a member of Intersil’ high performance A/D converter
family. The ICL7104-16, performs the analog switching and
digital function for a 16-bit binary A/D converter, with full
three-state output, UART handshake capability, and other
outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil’ integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including
±0
null indication), single reference operation,
very high input impedance, true input integration over a
constant period for maximum EMI rejection, fully
rationmetric operation, over-range indication, and a
medium quality built-in reference. The chip pair also offers
optional input buffer gain for high sensitivity applications, a
built-in clock oscillator, and output signals for providing an
external Auto-Zero capability in preconditioning circuitry,
synchronizing external multiplexers, etc.
Features
• 16-Bit/14-Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
• Ideally Suited for Interface to UARTs and
Microprocessors
• Conversion on Demand or Continuously
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage for True Ratiometric
Operation
• Onboard Clock and Reference
• Auto-Zero, Auto-Polarity
• Accuracy Guaranteed to 1 Count
• All Outputs TTL Compatible
•
±4V
Analog Input Range
• Status Signal Available for External Sync, A/Z in
Preamp, Etc.
Ordering Information
PART NUMBER
ICL8052CPD
lCL8052CDD
lCL8052ACPD
ICL8052ACDD
ICL8068CDD
ICL8068ACDD
lCL8068ACJD
ICL7104-14CPL
lCL7104-16CPL
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
14 Ld PDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld CERDIP
14 Ld CERDIP
14 Ld CERDIP
14 Ld CERDIP
40 Ld PDIP
40 Ld PDIP
PKG.
NO.
E14.3
F14.3
E14.3
F14.3
F14.3
F14.3
F14.3
E40.6
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3091.1
5-6
ICL8052/ICL7104, ICL8068/ICL7104
Pinouts
ICL8052/ICL8068
(CERDIP, PDIP)
TOP VIEW
V- 1
-1.2V
COMP OUT 2
REF CAP 3
REF BYPASS 4
GND 5
REF OUT 6
REF SUPPLY 7
V
REF
13 +BUFF IN
12 +INT IN
11 -INT IN
10 -BUFF IN
9 BUFF OUT
ICL8052/ 8 V++
ICL8068
14 INT OUT
ICL7104-16
V++
DIG GND
STTS
POL
OR
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
(OUTLINE DWGS DD, JD, PD)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
ICL7104-14
V++
1
DIG GND
STTS
POL
OR
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
NC
NC
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
2
3
4
5
6
7
8
9
10
ICL7104
(PDIP)
TOP VIEW
ICL7104-14
40 V-
39 COMP IN
38 REFCAP 1
37 V
REF
36 AZ
35 ANALOG
GND
34 REFCAP 2
33 BUF IN
32 ANALOG I/P
ICL7104-16
31 V+
ICL7104-14
(OUTLINE DWGS DL,
11
30 CE/LD
JL, PL)
12
29 SEN
13
14
15
16
17
18
19
20
28 R/H
27 MODE
26 CLK 2
25 CLK 1
24 CLK 3
23 HBEN
22 LBEN
21 BIT 1
HBEN
MBEN
Functional Block Diagram
+15V -15V
-BUF IN
REF
OUT
6
8
7
1
10
BUFFER
R
INT
BUF OUT
9
C
INT
-INT IN
11
INTEG.
INT OUT
14
COMP.
COMP
OUT
+5V
2
50kΩ
-15V
COUNTER
COMP IN
36
300kΩ
39
29 SEN
CONTROL LOGIC
27 MODE
28 R/H
LATCHES
BITS
OR POL 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
5
4
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
THREE-STATE OUTPUTS
24 HBEN
23 MBEN
22 LBEN
30 CE/LD
INT.
3 REF.
300pF
5kΩ
10kΩ 5
10µF
+BUF IN
-
A1
+
8052/8068
-
A2
+
-1.2V
+INT IN 12
C
AZ
AZ
-
A3
+
+BUF IN 13
33
SW3
V
REF
37
SW5
SW6
SW4
ANALOG
INPUT
ANALOG
GND
32
SW7
SW9
35
38
REF CAP (1)
C
REF
34
REF CAP (2)
SW8
SW2
7104
ZERO
CROSSING
DETECTOR
SW1
1
+15V
31
+5V
2
40
25
26
3
-15V CLOCK CLOCK STTS
(1)
(2)
FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM
5-7
ICL8052/ICL7104, ICL8068/ICL7104
Pin Descriptions
PIN NO.
1
2
3
SYMBOL
V++
GND
STTS
OPTION
DESCRIPTION
Positive Supply Voltage: Nominally +15V.
Digital Ground: 0V, ground return.
Status Output: HI during integrate and deintegrate until data is latched. LO when analog section
is in auto-zero configuration.
Polarity: Three-state output. HI for positive input.
Over Range: Three-state output.
-16
-14
-16
-14
-16
-14
-16
-14
-16
-14
-16
-14
-16
-14
-16
-14
4
5
6
POL
OR
BIT 16
BIT 14
BIT 15
BIT 13
BIT 14
BIT 12
BIT 13
BIT 11
BIT 12
BIT 10
BIT 11
BIT 9
BIT 10
NC
BIT 9
NC
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LBEN
Most Significant Bit (MSB).
DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true.
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Least Significant Bit (LSB).
LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30)
activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a
low byte flag output. See Figures 11, 12, 13.
-16
-14
-16
-14
MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22)
HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22)
HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22).
RC oscillator pin: Can be used as clock output.
23
MBEN
HBEN
24
HBEN
CLOCK3
5-8
ICL8052/ICL7104, ICL8068/ICL7104
Pin Descriptions
PIN NO.
25
26
27
SYMBOL
CLOCK 1
CLOCK 2
MODE
(Continued)
OPTION
Clock Input: External clock or ocsillator.
Clock Output: Crystal or RC oscillator.
INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly
controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure
13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered
and data output as in Figures 11 and 12 at conversion completion.
RUN/HOLD: Input HI conversions continuously performed every 2
17
(-16) or 2
15
(-14) clock
pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts
before input integrate.
SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates
‘send’.
CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable;
when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe
(-ve going) used in handshake mode. See Figures 11 and 12.
Positive Logic Supply Voltage: Nominally +5V.
Analog Input: High Side.
Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086).
Reference Capacitor: Negative Side.
Analog Ground: Input low side and reference low side.
Auto-Zero node.
Voltage Reference: Input (positive side).
Reference Capacitor: Positive side.
Comparator Input: From 8052/8068.
Negative Supply Voltage: Nominally -15V.
DESCRIPTION
28
R/H
29
SEN
30
CE/LD
31
32
33
34
35
36
37
38
39
40
V+
AN I/P
BUF IN
REFCAP2
AN. GND
A-Z
V
REF
REFCAP1
COMP-IN
V-
5-9
ICL8052/ICL7104, ICL8068/ICL7104
Absolute Maximum Ratings
ICL8052, ICL8068
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18V
Differential Input Voltage
(8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±30V
(8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±6V
Input Voltage (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±15V
Output Short Circuit Duration All Outputs (Note 3). . . . . . . Indefinite
ICL7104
V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
V++ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V
Positive Supply Voltage (GND to V++) . . . . . . . . . . . . . . . . . . . . 17V
Negative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . .-17V
Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to V-
Digital Input Voltage
(Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
14 Ld PDIP Package . . . . . . . . . . . . . .
100
N/A
40 Ld PDIP Package . . . . . . . . . . . . . .
60
N/A
14 Ld CERDIP Package . . . . . . . . . . .
75
20
Maximum Junction Temperature (Ceramic Package) . . . . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. For supply voltages less than
±15V,
the absolute maximum input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies to 70
o
C ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to
±100µA.
5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this
reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are
applied.
ICL7104 Electrical Specifications
PARAMETER
Clock Input, CLK 1
Comparator I/P, COMP IN (Note 6)
Inputs with Pulldown, MODE
V+ = +5V, V++ = +15V, V- = -15V, T
A
= 25
o
C, f
CLOCK
= 200kHz
SYMBOL
I
IN
I
IN
I
IH
I
IL
TEST
CONDITIONS
V
IN
= +5V to 0V
V
IN
= 0V to +5V
V
IN
= +5V
V
IN
= 0V
V
IN
= +5V
V
IN
= 0V
MIN
±2
-10
1
-10
-10
-30
2.5
-
I
OL
= 1.6mA
I
OH
= -10µA
I
OH
= -240µA
0
≤
V
OUT
≤
V+
-
-
2.4
-10
TYP
±7
±0.001
5
±0.01
±0.01
-5
2.0
1.5
0.27
4.5
3.5
±0.001
MAX
±30
10
30
10
10
-1
-
1.0
0.4
-
-
+10
UNITS
µA
µA
µA
µA
µA
µA
V
V
V
V
V
µA
Inputs with Pullups
SEN, R/H
LBEN, MBEN, HBEN, CE/LD (Note 7)
Input High Voltage, All Digital Inputs
Input Low Voltage, All Digital Inputs
Digital Outputs Three-Stated On,
LBEN, MBEN (16 Only), HBEN, CE/LD
BIT n, POL, OR (Note 8)
Digital Outputs Three-Stated Off
Bit n, POL, OR
Non Three-State Digital Output
STTS
I
IH
I
IL
V
IH
V
IL
V
OL
V
OH
V
OH
I
OL
V
OL
V
OH
I
OL
= 3.2mA
I
OH
= -400µA
I
OL
= 320µA
I
OH
= -320µA
I
OL
= 1.6mA
I
OH
= -320µA
-
2.4
-
-
-
2.4
0.3
3.3
0.5
4.5
0.27
3.5
0.4
-
-
-
0.4
-
V
V
V
V
V
V
Clock 2
V
OL
V
OH
Clock 3 (-14 Only)
V
OL
V
OH
5-10
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