LCK4953 datasheet, PDF - EEWORLD Datasheet

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LCK4953: DescriptionLow-Voltage PLL Clock Driver; File Size58KB，6 Pages; ManufacturerAgere System(LSI Logic)

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LCK4953 Overview

Low-Voltage PLL Clock Driver

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Data Sheet

November 2001

LCK4953

Low-Voltage PLL Clock Driver

Features

•

Fully integrated PLL

•

Output frequency up to 130 MHz in PLL mode

•

Nine outputs with high-impedance disable

32-lead TQFP

50 ps cycle-to-cycle jitter

Pin compatible with the

Motorola

MPC953 clock

driver

The LCK4953 is fully 3.3 V compatible and requires

no external loop filter components. All control inputs

accept LVCMOS or LVTTL compatible levels while

the outputs provide LVCMOS levels with the ability to

drive terminated 50

Ω

transmission lines. For series-

terminated 50

Ω

lines, each of the LCK4953 outputs

can drive two traces giving the device an effective

fan-out of 1:18. For the optimum combination of

board density and performance, the device is

packaged in a 7 mm

7 mm 32-lead TQFP package.

Table 1. Function Table

BYPASSB

Function

PLL Enabled

PLL Bypass

Function

Outputs Disabled

Outputs Enabled

Function

Description

The LCK4953 is a PLL-based clock driver device

intended for high-performance clock tree designs.

The LCK4953 is 3.3 V compatible with output

frequencies of up to 130 MHz and output skews of

75 ps. The LCK4953 can meet the most demanding

timing requirements and employs on-chip voltage

regulators to minimize cycle-to-cycle jitter and phase

jitter.

The LCK4953 is ideal for use as a zero delay, low

skew, fan-out buffer due to its differential LVPECL

reference input along with an external feedback

input. The MROEB pin of the LCK4953, when driven

high, will reset the internal counters and 3-state the

output buffers. The LCK4953 has been optimized for

zero delay performance.

MROEB

VCOSEL

PLLEN

Function

Select VCO

Select PELCLK

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