Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
General
The LCK4801 is a low-voltage, 3.3 V HSTL
differential clock synthesizer. The LCK4801 supports
two differential HSTL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multiple processor systems that
require HSTL differential inputs. The LCK4801
contains a fully integrated PLL (phase-locked loop)
which multiplies the HSTL_CLK or PECL_CLK input
frequency to match individual processor clock
frequencies. The PLL can be bypassed so that the
PCLK outputs are fed from the HSTL_CLK or
PECL_CLK input for test purposes. All outputs are
powered from a 2 V external supply to reduce on-
chip power consumption. All outputs are HSTL. The
PLL can operate in the internal feedback mode, or in
the external feedback mode for board level
debugging applications.
Features
s
s
s
s
s
s
Two fully selectable clock inputs.
Fully integrated PLL.
336 MHz to 1 GHz output frequencies.
HSTL outputs.
HSTL and LVPECL reference clocks.
32-pin TQFP package.
Description
PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)
TESTM (PULL-UP)
PLLREF_EN (PULL-UP)
REF_SEL (PULL-UP)
1
HSTL_CLK (PULL-UP)
HSTL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
(PULL-UP)
EXTFB_IN (HSTL)
(PULL-DOWN)
EXTFB_EN (PULL-UP)
EXTFB_OUT (HSTL)
SEL[4:0] (PULL-UP)
RESET (PULL-UP)
PLL_BYPASS (PULL-UP)
2274.a (F)
0
0
/M
1
0
1
/N
PLL
0
1
PCLK0
PCLK0 (HSTL)
PCLK1
PCLK1 (HSTL)
EXTFB_OUT
DECODE
Figure 1. LCK4801 Logic Diagram
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Description
(continued)
PLL_BYPASS
PLLREF_EN
V
DDHSTL
V
SS
RESET
SEL[4]
SEL[3]
SEL[2]
SEL[1]
SEL[0]
V
DDA
24
25
26
27
28
29
30
31
32
1
V
DDD
23
22
21
20
19
18
17
16
15
14
13
12
11
10
V
DDHSTL
PCLK0
PCLK0
PCLK1
PCLK1
EXTFB_OUT
EXTFB_OUT
V
DDHSTL
EXTFB_IN
EXTFB_IN
EXTFB_EN
PECL_CLK
PECL_CLK
2
TESTM
3
V
SS
4
PCLK0_EN
5
PCLK1_EN
6
REF_SEL
7
HSTL_CLK
8
HSTL_CLK
9
2275 (F)
Figure 2. 32-Pin TQFP
2
Agere Systems Inc.
Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
Pin Information
Table 1. Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
V
DDD
TESTM
V
SS
PCLK0_EN
PCLK1_EN
REF_SEL
HSTL_CLK
HSTL_CLK
PECL_CLK
PECL_CLK
EXTFB_EN
EXTFB_IN
EXTFB_IN
V
DDHSTL
EXTFB_OUT
EXTFB_OUT
V
DDHSTL
PCLK1
PCLK1
PCLK0
PCLK0
V
DDHSTL
PLLREF_EN
PLL_BYPASS
V
SS
RESET
SEL[4]
SEL[3]
SEL[2]
SEL[1]
SEL[0]
V
DDA
I/O
1
P
I
G
I
I
I
I
I
I
I
I
I
I
P
O
O
P
O
O
O
O
P
I
I
P
I
I
I
I
I
I
P
Type
Power Supply
LVCMOS
Ground
LVCMOS
LVCMOS
LVCMOS
Differential HSTL
Differential HSTL
Description
3.3 V power supply.
M divider test pins.
Digital ground.
PCLK0 enable.
PCLK1 enable.
Selects the PLL input reference clock.
PLL reference clock input.
PLL reference clock input.
Differential LVPECL PLL reference clock input.
Differential LVPECL PLL reference clock input.
LVCMOS
Differential HSTL
Differential HSTL
Power Supply
Differential HSTL
Differential HSTL
Power Supply
Differential HSTL
Differential HSTL
Differential HSTL
Differential HSTL
Power Supply
LVCMOS
LVCMOS
Ground
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power Supply
External feedback enable.
External feedback input.
External feedback input.
Output buffers power supply.
External feedback output clock.
External feedback output clock.
Output buffers power supply.
Output clock 1.
Output clock 1.
Output clock 0.
Output clock 0.
Output buffers power supply.
PLL reference enable.
Input signal PLL bypass.
Analog ground for PLL.
PLL bypass reset (for test use).
Selection of input and feedback frequency.
Selection of input and feedback frequency.
Selection of input and feedback frequency.
Selection of input and feedback frequency.
Selection of input and feedback frequency.
3.3 V filtered for PLL (PLL power supply).
1. P = power, I = input, G = ground, O = output.
Agere Systems Inc.
3
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Pin Information
(continued)
Table 2. Frequency Selection
Selection
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input
Divide
M
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Feedback
Divide
N
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
PCLK (MHz)
for Given Input Frequency (MHz)
70
336
350
364
378
392
406
420
434
448
462
476
490
504
518
532
546
560
564
588
602
616
630
644
658
672
686
700
714
728
742
756
770
100
480
500
520
540
560
580
600
620
640
660
680
700
720
740
760
780
800
820
840
860
880
900
920
940
960
980
1000
NA
NA
NA
NA
NA
120
576
600
624
648
672
696
720
744
768
792
816
840
864
888
912
936
960
984
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
125
600
625
650
675
700
725
750
775
800
825
850
875
900
925
950
975
1000
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
4
Agere Systems Inc.
Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
Pin Information
(continued)
Table 3. Function Control
Control Pin
REF_SEL
TESTM
PLLREF_EN
PLL_BYPASS
EXTFB_EN
PCLK0_EN
PCLK1_EN
RESET
SEL[4:0]
HSTL_CLK.
M divider test mode enabled.
Disable the input to the PLL and reset
the M divider.
Outputs fed by input reference or M
divider.
External feedback enabled.
PCLK0 = low, PCLK0 = high.
PCLK1 = low, PCLK1 = high.
Resets feedback N divider.
See Table 2 on page 4.
0
PECL_CLK.
Reference fed to bypass MUX.
Enable the input to the PLL.
Outputs fed by VCO.
Internal feedback enabled.
PCLK0 = high, PCLK0 = low.
PCLK1 = high, PCLK1 = low.
Feedback enabled.
See Table 2 on page 4.
1
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Input Voltage
Write Current
Storage Temperature
Symbol
V
DDD
/V
DDA
V
DDHSTL
V
IN
I
IN
T
S
Min
–0.5
–0.5
–0.5
–1
–50
Typical
—
—
—
—
—
Max
4.4
4.4
V
DDD
+ 0.3
1
150
Unit
V
V
mA
°C
Agere Systems Inc.
5
Embedded System
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