Ordering number : EN5545
MOS LSI
LC89977M
CCD Delay Line for PAL
Preliminary
Overview
The LC89977M is CCD delay line for PAL television
system that includes a chrominance signal crosstalk
exclusion filter and a luminance signal 1-H delay line on
chip.
Package Dimensions
unit: mm
3111-MFP14S
[LC89977M]
Features
• 5-V single-voltage power supply
• Built-in 3
×
PLL frequency multiplier circuit allows 3fsc
operation from an fsc (4.43 MHz) input.
• Can be switched between the PAL/GBI, and 4.43NTSC
formats by setting control pin values.
• Includes a built-in crosstalk exclusion comb filter for the
chrominance signal that provides high-precision comb
characteristics in an adjustment-free circuit.
• Peripheral circuits provided on chip for operation with a
minimum of external components.
• Positive-phase signal input, positive-phase signal output
(luminance signal)
SANYO: MFP14S
Functions
• CCD shift registers (for chrominance and luminance
signals)
• Timig generator and clock driver for CCD
• Delay time selective circuit
• CCD signal adder
• Auto-bias circuit
• Sync tip clamp circuit (luminance signal)
• Center bias circuit (chrominance signal)
• Sample-and-hold circuit
• 3
×
PLL frequency multiplier circuit
• 3fsc clock output circuit
• High voltage generator for CCD Reset Drain (RD)
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
Pd max
Topr
Tstg
Conditions
Ratings
–0.3 to +6.0
250
–10 to +60
–55 to +125
Unit
V
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N3096HA(OT) No. 5545-1/7
LC89977M
Allowable Operating Ranges
at Ta = 25°C
Parameter
Supply voltage
Clock input amplitude
Clock frequency
Chrominance signal input amplitude
Luminance signal input amplitude
Symbol
V
DD
V
CLK
F
CLK
V
IN-C
V
IN-Y
Sine wave
Conditions
Ratings
min
4.75
300
typ
5.00
500
4.43361875
350
400
500
572
max
5.25
1000
Unit
V
mVp-p
MHz
mVp-p
mVp-p
Pin Assignment
Block Diagram
No. 5545-2/7
LC89977M
Control Pin Functions
CONT
Low
High
Mode (representative)
PAL/GBI
4.43NTSC
Chrominance signal delay (number of CCD stages)
2H (1703.5) + 0H (1)
1H (845.5) + 0H (1)
Luminance signal delay (number of CCD stages)
1H (848)
1H (842)
Switching Voltage Levels
Parameter
Switching voltage level: low
Switching voltage level: high
Symbol
V
L
V
H
Conditions
Ratings
min
–0.3
2.0
typ
0.0
5.0
max
+0.5
6.0
Unit
V
V
Note:
*Since
the control pins have built-in pull-down resistors (about 70 kΩ), leaving these pins opens effectively sets them to the low level.
Function of the 3FSC Pin
This pin provides a 3fsc clock signal generated by the 3
×
PLL frequency multiplier circuit.
Electrical Characteristics
at V
DD
= 5.0 V, Ta = 25°C, F
CLK
= 4.43361875 MHz, V
CLK
= 500 mVp-p
Parameter
Symbol
I
DD-1
I
DD-2
V
INC-1
DC output voltage
V
INC-2
V
OUTC-1
V
OUTC-2
Voltage gain
G
VC-1
G
VC-2
C
D-1
C
D-2
L
NC-1
L
NC-2
L
CK3C-1
L
CK3C-2
L
CK1C-1
L
CK1C-2
N
C-1
N
C-2
Z
OC-1
Z
OC-2
T
DC-1
T
DC-2
Switch states
SW1
a
b
SW2
a
a
SW3
b
b
Test conditions
*1
*1
min
27
Ratings
typ
32
max
37
Unit
Supply current
mA
[Chrominance signal characteristics] (with no input to Y-IN)
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
a, b
a, b
b
b
*2
*2
*2
*2
*3
*3
*4
*4
*5
*5
*6
*6
*6
*6
*7
*7
*8
*8
*9
*9
200
–0.3
1.9
2.4
2.9
V
1.4
1.9
2.4
V
–2
0
+2
dB
Comb depth
–40
–35
dB
Linearity
0.0
+0.3
dB
Clock leakage (3fsc)
10
50
mVrms
Clock leakage (fsc)
0.5
1.5
mVrms
Noise
0.5
2.0
mVrms
Ω
ns
Output impedance
350
500
0-H delay time
130
Continued on next page.
No. 5545-3/7
LC89977M
Continued from preceding page.
Parameter
Symbol
Switch states
SW1
SW2
SW3
Test conditions
min
Ratings
typ
max
Unit
[Luminance signal characteristics] (With no signals input to C-IN1 and C-IN2)
V
INY-1
DC output voltage
V
INY-2
V
OUTY-1
V
OUTY-2
Voltage gain
G
VY-1
G
VY-2
G
FY-1
G
FY-2
D
GY-1
D
GY-2
D
PY-1
D
PY-2
L
SY-1
L
SY-2
L
CK3Y-1
L
CK3Y-2
L
CK1Y-1
L
CK1Y-2
N
Y-1
N
Y-2
Z
OY-1
Z
OY-2
T
DY-1
T
DY-2
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
a
a
b
a
a
a
a
a
a
b
b
a
a
a
a
a
a
a
a
a
a
a
a
a
b
a
a
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
c, b
c, b
b
b
*10
*10
*10
*10
*11
*11
*12
*12
*13
*13
*13
*13
*14
*14
*15
*15
*15
*15
*16
*16
*17
*17
*18
*18
250
1.3
1.8
2.3
V
0.7
1.2
1.7
V
–2
0
+2
dB
Frequency response
–2
0
+2
dB
Differential gain
0
5
8
%
Differential phase
0
5
8
deg
Linearity
37
40
43
%
Clock leakage (3fsc)
10
50
mVrms
Clock leakage (fsc)
0.5
1.5
mVrms
Noise
0.5
2.0
mVrms
Ω
µs
µs
Output impedance
400
63.81
63.36
550
Delay time
Test Conditions
1. The supply current with no input signal
2. The pin output voltage (the center bias voltage) with no input signal
3. Measure the C-OUT output when a 350-mVp-p sine wave is input to C-IN1 and C-IN2.
C-OUT output [mVp-p]
G
VC
= 20log —————————— [dB]
350 [mVp-p]
Test frequencies:
G
VC-1
: 4.429662 MHz (PAL/GBI)
G
VC-2
: 4.425694 MHz (4.43NTSC)
4. Measure the comb depth from the C-OUT output when a 350-mVp-p sine wave with frequency fa is input to C-IN1
and C-IN2, and when a sine wave of frequency fb is input.
The C-OUT output for an fb input [mVp-p]
C
D
= 20log —————————————————— [dB]
The C-OUT output for an fa input [mVp-p]
Test Frequencies
fa
fb
C
D-1
: 4.429662 MHz
4.425756 (PAL/GBI)
G
D-2
: 4.425694 MHz
4.417819 (4.43NTSC)
No. 5545-4/7
LC89977M
5. Measure the C-OUT output when a 200-mVp-p sine wave is input to C-IN1 and C-IN2, and when a 500-mVp-p sine
wave is input, and calculate the gain difference as follows:
The output for a 500-mVp-p input [mVp-p]
——————————————————
500 [mVp-p]
Test Frequencies
L
NC-1
4.429662MHz (PAL/GBI)
L
NC-2
4.425694MHz (4.43NTSC)
L
NC
= 20log
(
The output for a 200-mVp-p input [mVp-p]
—————————————————— [dB]
200 [mVp-p]
)
6. Measure the 3fsc (13.3 MHz) and fsc (4.43 MHz) components in the C-OUT output with no input signal.
7. Measure the noise in the C-OUT output with no input signal.
Measure the noise with a noise meter with a 200-kHz high-pass filter and a 5-MHz low-pass filter.
8. Input a 350-mVp-p sine wave to C-IN1 and C-IN2. Let V1 be the C-OUT output when SW3 is set to the ‘a’ position,
and let V2 be the C-OUT output when SW3 is set to the 'b' position.
V2 [mVp-p] – V1 [mVp-p]
Z
OC
= ———————————
×
500 [dB]
V1 [mVp-p]
Test Frequencies
Z
OC-1
: 4.429662 MHz (PAL/GBI)
Z
OC-2
: 4.425694 MHz (4.43NTSC)
9. The delay time in the C-OUT output with respect to the C-IN1 input. This is the CCD 1-bit delay.
10. The pin output voltage (clamp voltage) with no input signal.
11. Measure the Y-OUT output with a 200-kHz 400-mVp-p sine wave input to Y-IN.
Y-OUT output [mVp-p]
G
VY
= 20log —————————— [dB]
400 [mVp-p]
12. Measure the Y-OUT output when a 200-kHz 200-mVp-p sine wave is input to Y-IN, and when a 3.3-MHz
200-mVp-p sine wave is input.
The Y-OUT output for a 3.3-MHz input [mVp-p]
G
FY
= 20log ————————————————————— [dB]
The Y-OUT output for a 200-kHz input [mVp-p]
Here, adjust Vbias so that the clamp level is +250 mV.
13. Apply a 5-step staircase wave (as in the figure below) to Y-IN, and measure the differential gain and differential
phase in the Y-OUT output using a vector scope.
No. 5545-5/7
京公网安备 11010802033920号
EEWORLD
