Ordering number :
*EN5572
CMOS LSI
LC897194
CD-ROM Decoder with Built-In ATAPI (IDE) and DVD
ECC Interfaces
Preliminary
Overview
The LC897194 provides CD-ROM functionality and
includes built-in DVD ECC and ATAPI (IDE) interfaces.
Package Dimensions
unit: mm
3214-SQFP144
[LC897194]
Function
• CD-ROM ECC functionality, an ATAPI (IDE) interface
(the register and other blocks), and a DVD ECC
interface
Features
• ATAPI (IDE) interface
• DVD ECC interface
• Supports up to 12×-speed playback (when using 70-ns
16-bit data path DRAM)
• Transfer rate: 16.6 MB/s (when using 60-ns 16-bit data
path DRAM)
• Transfer rate: 8.33 MB/s (when using 70-ns 8-bit data
path DRAM)
• Between 1 and 32 Mbits of DRAM can be used as buffer
RAM.
• The user can freely set up the CD main channel and the
C2 flags in buffer RAM.
• Built-in batch transfer function (function for transferring
the CD main channel and the C2 flags in one operation)
• Built-in multiple transfer function (function for
automatically transferring multiple blocks in a single
operation)
SANYO: SQFP144
Specifications
Absolute Maximum Ratings
at V
SS
= 0 V
Parameter
Maximum supply voltage
I/O voltages
Allowable power dissipation
Operating temperature
Storage temperature
Soldering heat resistance (pins only)
Maximum I/O power
Note: Per basic I/O cell.
I
I
, I
O
max
Symbol
V
DD
max
V
I
, V
O
Pd max
Topr
Tstg
10 seconds
Ta = 25°C
Ta
≤
70°C
Conditions
Ta = 25°C
Ratings
–0.3 to +7.0
–0.3 to V
DD
+0.3
550
–30 to +70
–55 to +125
235
±20*
Unit
V
V
mW
°C
°C
°C
mA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5572-1/11
LC897194
Allowable Operating Ranges
at Ta = –30 to +70°C, V
SS
= 0 V
Parameter
Supply voltage
Input voltage range
Symbol
V
DD
V
IN
Conditions
Ratings
min
4.5
0
typ
5.0
max
5.5
V
DD
Unit
V
V
DC Characteristics
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 4.5 to 5.5 V
Parameter
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Input leakage current
Output leakage current
Pull-up resistance
Pull-down resistance
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IL3
V
IH4
V
IL4
V
IH5
V
IL5
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL5
I
IL
I
OZ
R
UP
R
DN
Applicable pins (see below)
TTL compatible: (1)
TTL compatible: (1)
TTL compatible, with pull-up resistor: (12)
TTL compatible, with pull-up resistor: (12)
TTL compatible, with pull-down resistor: (2)
TTL compatible, with pull-down resistor: (2)
TTL compatible, Schmitt characteristics: (3),
(5), (13), (14)
TTL compatible, Schmitt characteristics: (3),
(5), (13), (14)
CMOS compatible, Schmitt characteristics: (4)
CMOS compatible, Schmitt characteristics: (4)
I
OH
= –2 mA : (7), (10), (12)
I
OL
= 2 mA : (7), (10), (12)
I
OH
= –8 mA : (6)
I
OL
= 8 mA : (6)
I
OH
= –4 mA : (8), (13)
I
OL
= 24 mA : (8), (13)
I
OL
= 24 mA : (9), (14)
I
OL
= 2 mA : (11)
V
I
= V
SS
, V
DD
: (1), (2), (3), (4), (5), (12), (13),
(14)
When the output is high impedance: (9), (11),
(13), (14)
(12)
(2)
–10
–10
40
40
80
80
V
DD
– 2.1
0.4
0.4
0.4
+10
+10
160
160
V
DD
– 2.1
0.4
V
DD
– 2.1
0.4
0.8 V
DD
0.2 V
DD
2.5
0.6
2.2
0.8
2.2
0.8
Ratings
min
2.2
0.8
typ
max
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
kΩ
kΩ
Note: The applicable pins are as follows:
INPUT
(1) CSCTRL, RSSEL, HDB0 to 7, SUA0 to 6
(2) TEST0 to 4
(3) ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA, DA0 to 2, ZCS1FX, ZCS3FX
(4) ZCS, ZRD, ZWR
(5) ZDIOR, ZDIOW, DRESP, WFCK, SCOR
OUTPUT
(6) MCK, MCK2
(7) ZINT0, ZINT1
(8) DMARQ, HINTRQ
(9) IORDY, ZIOCS16
(10) RA0 to 9, ZCAS0 to 1, ZRAS0 to 1, ZLWE, ZUWE, ZOE, DREQ
(11) ZRSTCPU, ZRSTIC, ZSWAIT
INOUT
(12) D0 to 7, IO0 to 15
(13) DD0 to 15
(14) ZDASP, ZPDIAG
*:
The DC characteristics do not apply to the XTAL and XTALCK pins.
No. 5572-2/11
LC897194
Recommended Oscillator Circuit Example
R1 = 120 kΩ
R2 = 47
Ω
C1 = 30 pF
With a crystal with a resonant frequency of 16.9344 MHz, or:
R1 = 3.3 kΩ
R2 = None
C1 = 5 pF
With a crystal with a resonant frequency of 33.8688 MHz.
If third harmonics are a problem in the 33.8688-MHz recommended circuit, consult with the manufacturer of the crystal
for exact component values, since those values will be influenced by the printed circuit board used.
No. 5572-3/11
LC897194
Block Diagram
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
*11
**1
BCK, SDATA, LRCK, C2PO
DD0 to DD15, ZDASP, ZPDIAG
ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK
DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
D0 to D7
IO0 to IO15
RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE
DREQ
HDB0 to HDB7, DRESP
WFCK, SCOR
HISIDE (WD25C32) is made by WESTERN DIGITAL.
No. 5572-4/11
LC897194
Pin Functions
typ
I
O
Input
Output
B
P
Bidirection
Power
NC
Not connected
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Symbol
V
SS0
ZRAS0
ZRAS1
V
SS0
ZCAS0
ZCAS1
V
SS0
ZOE
ZUWE
ZLWE
RA0
RA1
RA2
RA3
RA4
RA5
RA6
V
DD
V
SS0
RA7
RA8
RA9
TEST0
TEST1
TEST2
TEST3
TEST4
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
SS0
V
DD
Type
P
O
O
P
O
O
P
O
O
O
O
O
O
O
O
O
O
P
P
O
O
O
NC
NC
NC
NC
NC
B
B
B
B
B
B
B
B
P
P
Data I/O to/from data buffer DRAM
Pull-up resistors are built in.
RA0 to RA9 are used for the data buffer DRAM address.
Buffer RAM output enable
Buffer RAM upper write enable
Buffer RAM lower write enable
RA0 to RA9 are used for the data buffer DRAM address.
Function
RAS signal output 0 to the buffer DRAM (Output 0 is normally used.)
RAS signal output 1 to the buffer DRAM
CAS signal output 0 to the buffer DRAM (Output 0 is normally used.)
CAS signal output 1 to the buffer DRAM
Used for testing. There should be no connections to these pins.
These pins must be left open.
Continued on next page.
No. 5572-5/11
TI Technology Forum
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