Ordering number : EN4079B
CMOS LSI
LC8901, 8901Q
Digital Audio Interface Receiver
Overview
The LC8901 and LC8901Q are LSIs for use in IEC958,
EIAJ CP-1201 format data transmission between digital
audio equipment. These LSIs are used on the receiving
side, and handle synchronization with the input signal and
demodulation of that signal to a normal format signal.
Package Dimensions
unit: mm
3025B-DIP42S
[LC8901]
Features
• On-chip PLL circuit synchronizes with the transmitted
IEC958, EIAJ CP-1201 format signal.
• Provides 20-bit LSB first and 16-bit MSB first audio
data output functions.
• Microprocessor interface for mode settings and code
output
• System clock can be selected to be either 384fs or 512fs.
• Provides both a digital source mode and an analog
source mode.
• Fabricated in a Si-gate CMOS process.
• 5 V single-voltage power supply
unit: mm
3148-QIP44M
[LC8901Q]
SANYO: DIP42S
SANYO: QIP44M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3095HA (OT)/52593JN/7202JN No. 4079-1/15
LC8901, 8901Q
Usage overview diagram
Assumes the use of both digital and analog source modes.
Digital source mode
Analog source mode
Pin Assignment
LC8901 (DIP42S)
LC8901Q (QIP44M)
No. 4079-2/15
LC8901, 8901Q
Block Diagram
No. 4079-3/15
LC8901, 8901Q
Pin Functions
LC8901 (DIP42S)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
DIN1
DIN2
DIN3
DIN4
DGND
DIN5
DIN6
DOUT1
DOUT2
RC1
RC2
LPF
STOP
TEST1
TEST2
AV
DD
R
AGND
VIN
VCO
DGND
CLK
XSYS
XIN1
XIN2
DV
DD
LOCK
ERROR
FS256
CLKOUT
EMPHA
BCLK
DATAOUT
LRCK
SUB1
SUB2
DO
DI
CE
CL
XMODE
DV
DD
I/O
I
I
I
I
—
I
I
O
O
I
O
I
I
I
I
—
I
—
I
O
—
I
I
I
O
—
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
—
Digital system ground
Data input pins without built-in amplifiers
Data input pins with built-in amplifiers
Pin function and circuit operation
Input data through output
RC oscillator connection
High: LPF time constant switching mode, low: fixed mode. This pin is normally high.
High: VCO operation stopped, low: normal operation
Test pins (These pins are normally low.)
Analog system power supply
VCO oscillator band adjustment
Analog system ground
VCO free-running oscillator setup
PLL low-pass filter
Digital system ground
Clock mode switching. High: 512fs, low: 384fs
Crystal mode setting. High: crystal mode
Crystal oscillator connection
Digital system power supply
High: PLL locked, low: unlocked
Error mute signal output
256fs clock output
VCO oscillator and crystal oscillator clock output
High: emphasis present, low: no emphasis
Bit clock output
Audio data output
Left/right clock output. High: left channel, low: right channel
Sampling frequency output
Microprocessor interface output
Microprocessor interface input
Microprocessor interface chip enable input
Microprocessor interface clock input
Used to start system operation after power on.
Digital system power supply
Note: The DIP42S package version has one fewer each of the digital system power supply and digital system ground pins than the QIP44M package version.
No. 4079-4/15
LC8901, 8901Q
LC8901Q (QIP44M)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
DIN5
DIN6
DOUT1
DOUT2
RC1
RC2
LPF
STOP
TEST1
TEST2
DV
DD
AV
DD
R
AGND
VIN
VCO
DGND
CLK
XSYS
XIN1
XIN2
DV
DD
LOCK
ERROR
FS256
CLKOUT
EMPHA
DGND
BCLK
DATAOUT
LRCK
SUB1
SUB2
DO
DI
CE
CL
XMODE
DV
DD
DIN1
DIN2
DIN3
DIN4
DGND
I/O
I
I
O
O
I
O
I
I
I
I
—
—
I
—
I
O
—
I
I
I
O
—
O
O
O
O
O
—
O
O
O
O
O
O
I
I
I
I
—
I
I
I
I
—
Digital system ground
Data input pins with built-in amplifiers
Data input pins without built-in amplifiers
Pin function and circuit operation
Input data through output
RC oscillator connection
High: LPF time constant switching mode, low: fixed mode. This pin is normally high.
High: VCO operation stopped, Low: normal operation
Test pins (These pins are normally low.)
Digital system power supply
Analog system power supply
VCO oscillator band adjustment
Analog system ground
VCO free-running oscillator setup
PLL low-pass filter
Digital system ground
Clock mode switching. High: 512fs, low: 384fs
Crystal mode setting. High: crystal mode
Crystal oscillator connection
Digital system ground
High: PLL locked, low: unlocked
Error mute signal output
256fs clock output
VCO oscillator and crystal oscillator clock output
High: emphasis present, low: no emphasis
Digital system ground
Bit clock output
Audio data output
Left/right clock output. High: left channel, low: right channel
Sampling frequency output
Microprocessor interface output
Microprocessor interface input
Microprocessor interface chip enable input
Microprocessor interface clock input
Used to start system operation after power on.
Digital system power supply
No. 4079-5/15
京公网安备 11010802033920号
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