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5962-9559505HYC

Description
Cache SRAM Module, 128KX32, 55ns, CMOS, CQFP68, CERAMIC, QFP-68
Categorystorage    storage   
File Size187KB,33 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

5962-9559505HYC Overview

Cache SRAM Module, 128KX32, 55ns, CMOS, CQFP68, CERAMIC, QFP-68

5962-9559505HYC Parametric

Parameter NameAttribute value
package instructionCERAMIC, QFP-68
Reach Compliance Codeunknown
Maximum access time55 ns
JESD-30 codeS-CQFP-F68
JESD-609 codee4
length39.625 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM MODULE
memory width32
Number of functions1
Number of terminals68
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height3.56 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
width39.625 mm
Base Number Matches1
REVISIONS
LTR
F
G
H
DESCRIPTION
Added device type 11. Added vendor CAGE code 0EU86 for device
types 05 through 09. -sld
Add note to paragraph 1.2.2 and table I, conditions. Add case
outline 9.
Correct figure 1, case outline M diagram, adding dimension "c", lead
thickness. Change figure 1, case outline M, A2 maximum dimension
from 0.015" to 0.025" and clarify A2 dimension in note 3.
Figure 1, case outline 9; changed the min limit for dimensions D2/E2
from 0.990 inches to 0.980 inches. Added vendor cage 88379 for the
case outline 9. Updated paragraph 1.2.3 to describe the five class
levels. -sld
Added device types 12 through 18. -sld
DATE (YR-MO-DA)
99-09-07
00-04-06
00-06-14
APPROVED
Raymond Monnin
Raymond Monnin
Raymond Monnin
J
01-05-06
Raymond Monnin
K
01-11-14
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
K
15
K
16
K
17
K
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
K
19
K
20
K
21
K
1
K
22
K
2
K
23
K
3
K
24
K
4
K
25
K
5
K
26
K
6
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
POST OFFICE BOX 3990
COLUMBUS, OHIO 43216-5000
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, STATIC RANDOM ACCESS
MEMORY, CMOS, 128K x 32-BIT
DRAWING APPROVAL DATE
95-07-19
REVISION LEVEL
K
SIZE
A
SHEET
CAGE CODE
67268
1 OF
26
5962-95595
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E622-01

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