Ordering number : EN5729A
CMOS IC
LC74786, 74786M, 74786JM
On-Screen Display Controller
Overview
The LC74786, LC74786M, and LC74786JM are on-
screen display controller CMOS ICs that display
characters and patterns on the TV screen under
microprocessor control. These ICs support 12
×
18-dot
characters and can display 12 lines by 24 characters of
text.
Package Dimensions
unit: mm
3067-DIP24S
[LC74786]
Features
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal)
×
18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128 (128 characters, one spacing
character, and one transparent spacing character)
• Initial display positions: 64 horizontal positions and 64
vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: About 1.0
second and about 0.5 second
• Blanking: Over the whole font (12
×
18 dots)
• Background color: 8 colors (internal synchronization
mode): 2f
SC
and 4f
SC
• Line background color
— Can be set for 3 lines
— Line background color: 8 colors (internal
synchronization mode): 2f
SC
and 4f
SC
• External control input: 8-bit serial input format
• On-chip sync separator circuit
• Video outputs - NTSC, PAL, PAL-N, PAL-M, NTSC
4.43, and PAL60 format composite video outputs
• Package
— 24-pin plastic DIP-24S (300 mil)
— 24-pin plastic MFP-24 (375 mil)
— 24-pin plastic MFP-24S (300 mil)
SANYO: DIP24S
unit: mm
3045B-MFP24
[LC74786M]
SANYO: MFP24
unit: mm
3112-MFP24S
[LC74786JM]
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
30698HA (OT) No. 5729-1/23
LC74786, 74786M, 74786JM
Pin Assignment
Pin Functions
Pin No.
1
2
Pin Name
V
SS
1
Xtal
IN
Xtal
OUT
(MUTE)
Crystal oscillator
(MUTE input)
Function
Ground
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to function as the
MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-
up resistor is built in and the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output.
This is a 3-value output.
Outputs the range signal specified by LNA*, LNB*, and LNC*. Outputs the crystal oscillator
clock when RST is low. (This signal is not output after a reset command is executed.)
Connections for the inductor and capacitor that form the character output dot clock generation
oscillator.
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a
high level when synchronizing signals are present.
Outputs the dot clock (LC oscillator) when RST is low. (This signal is not output on command
resets.)
Serial data input circuit enable pin. Serial data input is enabled when a low level is input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Serial data input circuit clock input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Serial data input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Composite video signal level adjustment power supply (analog system power supply)
Notes
3
4
CTRL1
(CHABLK)
Crystal oscillator input switching
(CHABLK output)
5
6
7
HFTON
OUT
OSC
IN
OSC
OUT
Background line output
LC oscillator
8
SYNC
JDG
External synchronizing signal
judgment output
9
10
11
12
CS
SCLK
SIN
V
DD
2
Enable input
Clock input
Data input
Power supply
Continued on next page.
No. 5729-2/23
LC74786, 74786M, 74786JM
Continued from preceding page.
Pin No.
13
14
15
16
17
Pin Name
CV
OUT
V
SS
2
CV
IN
V
DD
1
SYN
IN
Function
Video signal output
Ground
Video signal input
Power supply
Sync separator circuit input
Sync separator circuit bias
voltage
Composite synchronizing
signal output
Composite video signal output
Ground connection (analog system ground)
Composite video signal input
Power supply (+5 V: digital system power supply)
Video signal input to the internal sync separator circuit (Used as either the horizontal
synchronizing signal or the composite synchronizing signal input when the internal sync
separator circuit is not used.)
Internal sync separator circuit bias voltage monitor
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the SEL0 and MOD0 setting.
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output signal.
An integration circuit must be connected to the SEP
OUT
pin. This pin must be tied to V
DD
1 if
unused. This pin can be switched to function as the frame signal input mode by setting SEL1
high. This is valid when CTL3 is set high. This input has hysteresis characteristics.
Pin settings take priority for switching between the NTSC, PAL, PAL-M, PAL-N, NTSC 4.43,
and PAL60 video formats. The NTSC format is selected when this pin is low after a reset.
The command video format (NTSC, PAL, PAL-M, PAL-N, NTSC 4.43, or PAL60) selection is
valid. The PAL-M format is selected when this pin is high.
Background color phase adjustment. Connect a resistor between this pin and ground.
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Power supply (+5 V: digital system power supply)
Notes
18
19
SEP
C
SEP
OUT
20
SEP
IN
Vertical synchronizing signal input
21
CTRL2
NTSC/PAL-M selection input
22
23
24
CDLR
RST
V
DD
1
Background color phase
adjustment
Reset input
Power supply (+5 V)
Note: Both V
DD
1 pins must be connected to the power supply.
No. 5729-3/23
LC74786, 74786M, 74786JM
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
max
V
IN
max
V
OUT
max
Pd max
Topr
Tstg
V
DD
1 and V
DD
2
All input pins
HFTON
OUT
, SYNC
JDG
, and SEP
OUT
Ta = 25°C
Conditions
Ratings
V
SS
–0.3 to V
S
+6.5
V
S
–0.3 to V
DD
+0.3
V
SS
–0.3 to V
DD
+0.3
350
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
Allowable Operating Ranges
Parameter
Symbol
V
DD
1
V
DD
2
V
IH
1
V
IH
2
V
IL
1
V
IL
2
R
PU
V
IN
1
V
IN
2
V
IN
3
V
DD
1
V
DD
2
RST, CS, SIN, SCLK, SEP
IN
, and MUTE
CTRL1 and CTRL2
RST, CS, SIN, SCLK, SEP
IN
, and MUTE
CTRL1 and CTRL2
RST, CS, SIN, SCLK, and MUTE
Applies to pins set up by options.
CV
IN
: V
DD
1 = 5 V
SYN
IN
: V
DD
1 = 5 V
Xtal
IN
(when used for external clock input)
f
IN
= 2fsc or 4fsc ; V
DD
1 = 5 V
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: NTSC)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: NTSC)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL)
Oscillator frequencies
F
OSC
1
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL-M)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL-M)
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL-N)
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL-N)
F
OSC
2
OSC
IN
and OSC
OUT
oscillator pins (LC oscillator)
5
Note: Applications must be especially cautious about noise when using the Xtal
IN
input pin in clock input mode.
0.10
7.159
14.318
8.867
17.734
7.151
14.302
7.164
14.328
10
Conditions
Ratings
min
4.5
4.5
0.8 V
DD
1
0.7 V
DD
1
V
SS
– 0.3
V
SS
– 0.3
25
50
2.0
2.0
2.5
5.0
typ
5.0
5.0
max
5.5
1.27 V
DD
1
V
DD
1+0.3
V
DD
1+0.3
0.2 V
DD
1
0.3 V
DD
1
90
Unit
V
V
V
V
V
V
kΩ
Vp-p
Vp-p
Vp-p
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Supply voltage
Input high-level voltage
Input low-level voltage
Pull-up resistance
Composite video signal input voltage
Input voltage
No. 5729-4/23
LC74786, 74786M, 74786JM
Electrical Characteristics
at Ta = –30 to +70°C. V
DD
1 = 5 V unless otherwise specified.
Parameter
Input off leakage current
Output off leakage current
Output high-level voltage
Output low-level voltage
Symbol
I
leak1
I
leak2
V
OH
1
V
OL
1
CV
IN
CV
OUT
HFTON
OUT
, SYNC
JDG
, and SEP
OUT
HFTON
OUT
, SYNC
JDG
, and SEP
OUT
V
DD
1 = 4.5 V,
I
OH
= –1.0 mA
V
DD
1 = 4.5 V,
I
OL
= –1.0 mA
H
Three-value output voltage
V
O
CHABLK
V
DD
1 = 5.0 V
M
L
I
IH
I
IL
I
DD
1
I
DD
2
SYNC level
V
SN
RST, CS, SIN, SCLK, CTRL1,
SEP
IN
, and MUTE
CTRL1 and OSC
IN
V
DD
1
V
DD
2
V
IN
= V
DD
1
V
IN
= V
SS
1
All outputs: open
Xtal:7.159 MHz
LC:8 MHz
V
DD
2 = 5 V
(1)
(2)
(3)
(1)
Pedestal level
V
PD
(2)
(3)
(1)
Color burst low level
V
CBL
(2)
(3)
(1)
Color burst high level
V
CBH
(2)
(3)
(1)
Background color low level (other than blue)
V
RSL
0
(2)
(3)
(1)
Background color high level (other than blue)
V
RSH
0
CV
OUT
(1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
Blue background 1 low level
V
RSL
1
(3): When the sync level = 1.3 V
(2)
V
DD
1 = 5.0 V (3)
V
DD
2 = 5.0 V (1)
(2)
(3)
(1)
Blue background 2 low level
V
RSL
2
(2)
(3)
(1)
Blue background 1 and 2 high level
V
RSH
1, 2
(2)
(3)
(1)
Frame level 0
V
BK
0
(2)
(3)
(1)
Frame level 1
V
BK
1
(2)
(3)
(1)
Character level
V
CHA
(2)
(3)
Note: Blue background 1 or 2 are option settings.
0.70
0.89
1.18
1.32
1.52
1.81
0.98
1.17
1.46
1.63
1.83
2.11
1.17
1.36
1.65
2.33
2.52
2.81
1.08
1.27
1.56
1.49
1.68
1.97
1.97
2.17
2.46
1.40
1.60
1.89
1.97
2.17
2.46
2.55
2.75
3.04
0.82
1.01
1.30
1.44
1.64
1.93
1.10
1.29
1.58
1.75
1.95
2.23
1.29
1.48
1.77
2.45
2.64
2.93
1.20
1.39
1.68
1.61
1.80
2.09
2.09
2.29
2.58
1.52
1.72
2.01
2.09
2.29
2.58
2.67
2.87
3.16
–1
15
20
0.94
1.13
1.42
1.56
1.76
2.05
1.22
1.41
1.70
1.87
2.07
2.35
1.41
1.60
1.89
2.57
2.76
3.05
1.32
1.51
1.80
1.83
1.92
2.21
2.21
2.41
2.70
1.64
1.84
2.13
2.21
2.41
2.70
2.79
2.99
3.28
V
V
V
V
V
V
V
V
V
V
V
V
3.3
1.8
0
3.5
1.0
5.0
2.3
0.8
1
Pin
Conditions
Ratings
min
typ
max
1
1
Unit
µA
µA
V
V
V
V
V
µA
µA
mA
mA
Input current
Operating mode current drain
No. 5729-5/23
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