Ordering number : EN5745
CMOS IC
LC72706E
FM Multiplex Receiver IC Supporting
All Worldwide Standards
Overview
The LC72706E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. In conjunction with a bandpass filter IC
(either the LV3400M or the LV3403M), the LC72706E
can form a compact yet high-functionality FM multiplex
reception system. This IC supports all the FM multiplex
frame structures (methods A, B, and C) in the ITU-R
recommendations.
Package Dimensions
unit: mm
3148-QFP44MA
[LC72706E]
Applications
• Receivers for DARC format mobile receiver FM
multiplex broadcasts
Functions
• MSK delay detection circuit based on a 1T delay
• Error correction function based on a 2T delay (in the
MSK detector stage)
• Digital PLL based clock regeneration circuit
• Shift-register type 1T and 2T delay circuits
• Block and frame synchronization detection circuit
• Serial control data transfer based support for the A, B,
and C FM multiplex frame structures
• Function for setting the number of allowable BIC errors,
the number of synchronization protection.
• Error correction using (272, 190) codes
• Layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2-MHz crystal oscillator circuit
SANYO: QFP44MA
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40698RM (OT) No. 5745-1/15
LC72706E
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Maximum supply voltage
Input voltage
Symbol
V
DD
max
V
IN
1
V
IN
2
V
OUT
1
V
OUT
2
I
OUT
Pd max
Topr
Tstg
CE, CL, DI, RST, STNBY
Pins other than V
IN
1
DO
Pins other than V
OUT
1
BLOCK, FLOCK, DO
Ta
≤
85°C
Conditions
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to V
DD
+0.3
–0.3 to +7.0
–0.3 to V
DD
+0.3
0 to 4.0
400
–40 to +85
–55 to +125
Unit
V
V
V
V
V
mA
mW
°C
°C
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Allowable Operating Ranges
at Ta = –40 to 85°C, V
SS
= 0 V
Parameter
Supply voltage
Input high-level voltage
Symbol
V
DD
V
IH
1
V
IH
2
V
IL
1
V
IL
2
F
OSC
V
XI
Input sensitivity
V
XI
[Serial I/O*]
Clock low-level time
Clock high-level time
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
Layer 4 CRC change time
Note
*:
See the serial data timing chart.
t
CL
t
CH
t
SU
t
HD
t
EL
t
ES
t
EH
t
LC
t
DD0
t
CRC
CL
CL
CL, DI
CL, DI
CL, CE
CL, CE
CL, CE
CE
DO, CL
CRC4, CL
277
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
555
0.7
µs
µs
µs
µs
µs
µs
µs
µs
ns
µs
CL, CE, DI, RST, STNBY
MSK
Applies to the same pins as V
IH
1
Applies to the same pins as V
IH
2
This IC operates at frequencies within a
±250 ppm precision.
With a capacitance-coupled sine wave input
to X
IN
V
DD
= +4.5 V to 5.5 V
With a capacitance-coupled sine wave input
to X
IN
V
DD
= +2.7 V to 3.6 V
400
Conditions
Ratings
min
2.7
0.7 V
DD
0.7 V
DD
V
SS
V
SS
7.2
typ
max
5.5
5.5
V
DD
0.3 V
DD
0.3 V
DD
Unit
V
V
V
V
V
MHz
Input low-level voltage
Oscillator frequency
1500
mVrms
400
900
mVrms
Electrical Characteristics (1)
at V
DD
= +4.5 to +5.5 V, in the allowable operating ranges
Parameter
Symbol
V
OH
1
Output high-level voltage
V
OH
2
V
OL
1
Output low-level voltage
V
OL
2
V
OL
3
Input high-level current
I
IH
1
I
IH
2
I
IL
I
OFF
V
HIS
R
f
I
DD
Conditions
I
O
= 1 mA, FLICK
I
O
= 2 mA, BLOCK, FLOCK, INT, CLK16,
DATA
I
O
= 1 mA, applies to the same pins as V
OH
1
I
O
= 2 mA, applies to the same pins as V
OH
2
I
O
= 2 mA, DO
V
IN
= 5.5 V, CE, CL, DI, RST, STNBY
V
IN
= V
DD
, input pins other than I
IH
1
V
IN
= V
SS
, MSK, CL, CE, DI, RST, STNBY,
TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST
V
O
= V
DD
, DO
MSK, CL, CE, DI, RST, STNBY
X
IN
, X
OUT
0.1 V
DD
1.0
16
25
Ratings
min
V
DD
– 1.0
V
DD
– 0.4
1.0
0.4
0.4
1.0
1.0
–1
5
typ
max
Unit
V
V
V
V
V
µA
µA
µA
µA
V
MΩ
mA
Input low-level current
Output off leakage current
Hysteresis voltage
Internal feedback resistor
Current drain
No. 5745-2/15
LC72706E
Electrical Characteristics (2)
at V
DD
= +2.7 to +3.6 V, in the allowable operating ranges
Parameter
Symbol
V
OH
1
Output high-level voltage
V
OH
2
V
OL
1
Output low-level voltage
V
OL
2
V
OL
3
Input high-level current
Input low-level current
Output off leakage current
Hysteresis voltage
Internal feedback resistor
Current drain
I
IH
1
I
IH
2
I
IL
I
OFF
VHIS
R
f
I
DD
Conditions
I
O
= 0.5 mA, FLICK
I
O
= 1 mA, BLOCK, FLOCK, INT, CLK16,
DATA
I
O
= 0.5 mA, applies to the same pins as V
OH
1
I
O
= 1 mA, applies to the same pins as V
OH
2
I
O
= 1 mA, DO
V
IN
= 5.5 V, CE, CL, DI, RST, STNBY
V
IN
= V
DD
, input pins other than I
IH
1
V
IN
= V
SS
, MSK, CL, CE, DI, RST, STNBY,
TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST
V
O
= V
DD
, DO
MSK, CL, CE, DI, RST, STNBY
X
IN
, X
OUT
0.1 V
DD
2.5
8
12
Ratings
min
V
DD
– 1.0
V
DD
– 0.4
1.0
0.4
0.4
1.0
1.0
–1
1
typ
max
Unit
V
V
V
V
V
µA
µA
µA
µA
V
MΩ
mA
Block Diagram
MSK signal input
1T delay
Clock
regeneration
2T delay
MSK
correction
PN
decoding
Synchronization
regeneration
Timing
control
Error
correction
Layer 2 CRC
Data
Address
Memory array
Layer 4 CRC
Output control
(CPU interface)
Pin Assignment
No. 5745-3/15
LC72706E
Pin Functions
Pin No.
7
26
27
28
32
30
44
9
12
13
14
15
16
17
18
19
6
8
20
21
4
10
11
23
22
24
25
34
35
36
37
39
41
42
43
Pin Name
MSK
CL
CE
DI
RST
STNBY
TEST
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TPC1
TPC2
TOSEL1
TOSEL2
FLICK
CLK16
DATA
BLOCK
FLOCK
CRC4
INT
IC0
IC1
IC2
IC3
IC4
IC5
IC6
IC7
Internal connections. These pins must be left open.
Reference clock output for the LV3400M/03M
Clock regeneration monitor
Demodulated data monitor
Outputs a high level during block synchronization.
Outputs a high level during frame synchronization.
Layer 4 CRCC check result output
External CPU interrupt signal
Output
Must be connected to either V
DD
or V
SS
.
Input
Function
76-kHz MSK signal input (from the LV3400M/03M)
CCB serial interface
Clock input
Data control input
Data input
System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)
Input
I/O
Circuit type
29
DO
Data output used by the CCB serial interface
Output
1
2
XIN
XOUT
System clock generation crystal oscillator element connections
Input
Output
5, 31, 38
3, 33, 40
V
DD
V
SS
Power supply (+2.7 to 5.5 V)
Ground
—
—
No. 5745-4/15
LC72706E
Data I/O Techniques
• CCB Technique
Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.
I/O mode
Input
Output
Input
Address
B0
0
1
0
B1
1
1
0
B2
0
0
1
B3
1
1
1
A0
1
1
1
A1
1
1
1
A2
1
1
1
A3
1
1
1
16-bit control data input
Data output for the input clock (CL)
Data input (in 8-bit units) for the layer 4 CRC check circuit
Function
I/O mode determined
Data Input Timing
Internal data latching
Data Output Timing
Note:The DO pin is normally left open.
Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.
No. 5745-5/15
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